Correlating Device Behaviors with Semiconductor Lattice Damage at MOS Interface by Comparing Plasma-etching and Regrown Recessed-gate Al2O3/GaN MOS-FETs

AbstractA highly sensitive laser probe for photo-acoustic displacement(PAD) has been developed and applied to the monitoring of low-level lattice damage in semiconductors. Since a photodisplacement laser probe with the sensitivity of 0.1 picometers is employed in this measurement, lower density damage for instance, formed by 50 keV B+ implantation with a dose of 5X109 ions/cm2 can be detected. Correlation of the PAD with damage density was obtained in B+ implantation. Therefore, quantitative damage density can be obtained from the relation for lightly damaged layers, such as formed by chemomechanical polishing and by electron cyclotron resonance plasma etching. This technique is useful-for monitoring of low damage density surface.

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Diamond ThinFilm Recessed Gate FieldEffect Transistors Fabricated by Electron Cyclotron Resonance Plasma Etching

High-Temperature Electronics ◽

10.1109/9780470544884.ch60 ◽

2009 ◽

Keyword(s):

Plasma Etching ◽

Cyclotron Resonance ◽

Electron Cyclotron Resonance ◽

Electron Cyclotron ◽

Electron Cyclotron Resonance Plasma ◽

Recessed Gate ◽

Resonance Plasma

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Analytical Electron Microscopy of Surface-Modified Ceramics

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100118291 ◽

1985 ◽

Vol 43 ◽

pp. 276-279

Author(s):

P. S. Sklad

Keyword(s):

Electron Microscopy ◽

Analytical Electron Microscopy ◽

Theoretical Models ◽

Ceramic Materials ◽

Solute Concentration ◽

Second Phase ◽

Analytical Electron ◽

Implantation Techniques ◽

Lattice Damage ◽

Surface Modified

Over the past several years, it has become increasingly evident that materials for proposed advanced energy systems will be required to operate at high temperatures and in aggressive environments. These constraints make structural ceramics attractive materials for these systems. However it is well known that the condition of the specimen surface of ceramic materials is often critical in controlling properties such as fracture toughness, oxidation resistance, and wear resistance. Ion implantation techniques offer the potential of overcoming some of the surface related limitations.While the effects of implantation on surface sensitive properties may be measured indpendently, it is important to understand the microstructural evolution leading to these changes. Analytical electron microscopy provides a useful tool for characterizing the microstructures produced in terms of solute concentration profiles, second phase formation, lattice damage, crystallinity of the implanted layer, and annealing behavior. Such analyses allow correlations to be made with theoretical models, property measurements, and results of complimentary techniques.

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Using the secondary electrons (SE) of SEM with NIST‘s MONSEL-II program to obtain improved linewidth measurements and slope angles of line edges on a MMIC GaAs device

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100167184 ◽

1996 ◽

Vol 54 ◽

pp. 944-945

Author(s):

Richard G. Sartore

Keyword(s):

Integrated Circuits ◽

Plasma Etching ◽

Microwave Integrated Circuits ◽

Monolithic Microwave Integrated Circuits ◽

Thick Gold ◽

Gaas Devices ◽

Source Distance ◽

Margin Of Error ◽

Dimensional Measurements ◽

Barrier Metal

In the evaluation of GaAs devices from the MMIC (Monolithic Microwave Integrated Circuits) program for Army applications, there was a requirement to obtain accurate linewidth measurements on the nominal 0.5 micrometer gate lengths used to fabricate these devices. Preliminary measurements indicated a significant variation (typically 10 % to 30% but could be more) in the critical dimensional measurements of the gate length, gate to source distance and gate to drain distance. Passivation introduced a margin of error, which was removed by plasma etching. Additionally, the high aspect ratio (4-5) of the thick gold (Au) conductors also introduced measurement difficulties. The final measurements were performed after the thick gold conductor was removed and only the barrier metal remained, which was approximately 250 nanometer thick platinum on GaAs substrate. The thickness was measured using the penetration voltage method. Linescan of the secondary electron signal as it scans across the gate is shown in Figure 1.

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Silicon layers grown over SiO2 by liquid phase epitaxy: Electron Microscopical study

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s042482010017596x ◽

1990 ◽

Vol 48 (4) ◽

pp. 566-567

Author(s):

F. Banhart ◽

F.O. Phillipp ◽

R. Bergmann ◽

E. Czech ◽

M. Konuma ◽

...

Keyword(s):

Electron Microscopy ◽

Liquid Phase ◽

Plasma Etching ◽

Liquid Phase Epitaxy ◽

Three Dimensional ◽

Microscopical Study ◽

Sample Temperature ◽

Structural Defects ◽

Si Substrates ◽

Etched Surface

Defect-free silicon layers grown on insulators (SOI) are an essential component for future three-dimensional integration of semiconductor devices. Liquid phase epitaxy (LPE) has proved to be a powerful technique to grow high quality SOI structures for devices and for basic physical research. Electron microscopy is indispensable for the development of the growth technique and reveals many interesting structural properties of these materials. Transmission and scanning electron microscopy can be applied to study growth mechanisms, structural defects, and the morphology of Si and SOI layers grown from metallic solutions of various compositions.The treatment of the Si substrates prior to the epitaxial growth described here is wet chemical etching and plasma etching with NF3 ions. At a sample temperature of 20°C the ion etched surface appeared rough (Fig. 1). Plasma etching at a sample temperature of −125°C, however, yields smooth and clean Si surfaces, and, in addition, high anisotropy (small side etching) and selectivity (low etch rate of SiO2) as shown in Fig. 2.

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Continuum Fluid Models for Plasma Etching Reactor Control

1993 American Control Conference ◽

10.23919/acc.1993.4793455 ◽

1993 ◽

Author(s):

Mark Wilcoxson ◽

Vasilios Manousiouthakis

Keyword(s):

Plasma Etching ◽

Fluid Models ◽

Reactor Control

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Metal-Assisted Plasma Etching of Silicon: A Liquid-Free Alternative to MACE

10.26434/chemrxiv.6128237 ◽

2018 ◽

Author(s):

Julia Sun ◽

Benjamin Almquist

Keyword(s):

Liquid Phase ◽

Plasma Etching ◽

Chemical Etching ◽

Gold Films ◽

Metallic Films ◽

Au Catalyst ◽

Feed Concentration ◽

Catalytic Activities ◽

Metal Assisted Chemical Etching ◽

Complex Nanostructures

For decades, fabrication of semiconductor devices has utilized well-established etching techniques to create complex nanostructures in silicon. Of these, two of the most common are reactive ion etching in the gaseous phase and metal-assisted chemical etching (MACE) in the liquid phase. Though these two methods are highly established and characterized, there is a surprising scarcity of reports exploring the ability of metallic films to catalytically enhance the etching of silicon in dry plasmas via a MACE-like mechanism. Here, we discuss a metal-assisted plasma etch (MAPE) performed using patterned gold films to catalyze the etching of silicon in an SF6/O2 mixed plasma, selectively increasing the rate of etching by over 1000%. The degree of enhancement as a function of Au catalyst configuration and relative oxygen feed concentration is characterized, along with the catalytic activities of other common MACE metals including Ag, Pt, and Cu. Finally, methods of controlling the etch process are briefly explored to demonstrate the potential for use as a liquid-free fabrication strategy.

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Development of Backside Scanning Capacitance Microscopy Technique for Advanced SOI Microprocessors

ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2006p0094 ◽

2006 ◽

Author(s):

Vinod Narang ◽

P. Muthu ◽

J.M. Chin ◽

Vanissa Lim

Keyword(s):

Plasma Etching ◽

Data Interpretation ◽

Parameters Optimization ◽

Scanning Capacitance Microscopy ◽

Microscopy Technique ◽

Thermal Oxide ◽

Specific Analysis ◽

Thin Oxide ◽

P Type ◽

Uv Ozone

Abstract Implant related issues are hard to detect with conventional techniques for advanced devices manufactured with deep sub-micron technology. This has led to introduction of site-specific analysis techniques. This paper presents the scanning capacitance microscopy (SCM) technique developed from backside of SOI devices for packaged products. The challenge from backside method includes sample preparation methodology to obtain a thin oxide layer of high quality, SCM parameters optimization and data interpretation. Optimization of plasma etching of buried oxide followed by a new method of growing thin oxide using UV/ozone is also presented. This oxidation method overcomes the limitations imposed due to packaged unit not being able to heat to high temperature for growing thermal oxide. Backside SCM successfully profiled both the n and p type dopants in both cache and core transistors.

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