High-current recessed gate enhancement-mode ultrawide bandgap Al x Ga1−x N channel MOSHFET with drain current 0.48 A mm−1 and threshold voltage +3.6 V

2021 ◽  
Vol 14 (1) ◽  
pp. 014003
Author(s):  
Shahab Mollah ◽  
Kamal Hussain ◽  
Abdullah Mamun ◽  
Mikhail Gaevski ◽  
Grigory Simin ◽  
...  
2005 ◽  
Vol 41 (7) ◽  
pp. 449 ◽  
Author(s):  
W.B. Lanford ◽  
T. Tanaka ◽  
Y. Otoki ◽  
I. Adesida

2012 ◽  
Vol 717-720 ◽  
pp. 1059-1064 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Lin Cheng ◽  
Sarit Dhar ◽  
Craig Capell ◽  
Charlotte Jonas ◽  
...  

We present our recent developments in 4H-SiC power DMOSFETs. 4H-SiC DMOSFETs with a room temperature specific on-resistance of 3.7 mΩ-cm2 with a gate bias of 20 V, and an avalanche voltage of 1550 V with gate shorted to source, was demonstrated. A threshold voltage of 3.5 V was extracted from the power DMOSFET, and a subthreshold swing of 200 mV/dec was measured. The device was successfully scaled to an active area of 0.4 cm2, and the resulting device showed a drain current of 377 A at a forward voltage drop of 3.8 V at 25oC.


2011 ◽  
Vol 130-134 ◽  
pp. 3392-3395 ◽  
Author(s):  
Gang Chen ◽  
Peng Wu ◽  
Song Bai ◽  
Zhe Yang Li ◽  
Yun Li ◽  
...  

. Silicon carbide (SiC) SITs were fabricated using home-grown epi structures. The gate is a recessed gate - bottom contact (RG - B). We designed that the mesa space 2.7μm and the gate channel is 1.2μm. One cell has 400 source fingers and each source finger width is 100μm. 1mm SiC SIT yielded a current density of 123mA/mm of drain current at a drain voltage of 20V. A maximum current density of 150 mA/mm was achieved with Vd=40V. The device blocking voltage with a gate bias of-16 V was 200 V. Packaged 24-cm devices were evaluated using amplifier circuits designed for class AB operations. A total power output in excess of 213 W was obtained with a power density of 8.5 W/cm and gain of 8.5 dB at 500 MHz under pulse operation.


2021 ◽  
Author(s):  
Rishu Chaujar ◽  
Mekonnen Getnet Yirak

Abstract In this work, junctionless double and triple metal gate high-k gate all around nanowire field-effect transistor-based APTES biosensor has been developed to study the impact of ITCs on device sensitivity. The analytical results were authenticated using ‘‘ATLAS-3D’’ device simulation tool. Effect of different interface trap charge on the output characteristics of double and triple metal gate high-k gate all around junctionless NWFET biosensor was studied. Output characteristics, like transconductance, output conductance,drain current, threshold voltage, subthreshold voltage and switching ratio, including APTES biomolecule, have been studied in both devices. 184% improvement has been investigated in shifting threshold voltage in a triple metal gate compared to a double metal gate when APTES biomolecule immobilizes on the nanogap cavity region under negative ITCs. Based on this finding, drain off-current ratio and shifting threshold voltage were considered as sensing metrics when APTES biomolecule immobilizes in the nanogap cavity under negative ITCs which is significant for Alzheimer's disease detection. We signifies a negative ITC has a positive impact on our proposed biosensor device compared to positive and neutral ITCs.


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