Thermal design and management of micro-pin fin heat sinks for energy-efficient three-dimensional stacked integrated circuits

2021 ◽  
Vol 175 ◽  
pp. 121192
Author(s):  
Daewoong Jung ◽  
Haeun Lee ◽  
Daeyoung Kong ◽  
Eunho Cho ◽  
Ki Wook Jung ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Energy Efficient ◽  
Three Dimensional ◽  
Thermal Design ◽  
Heat Sinks ◽  
Pin Fin ◽  
Stacked Integrated Circuits

scholarly journals Meta-Study on Integrated Cooling of Modern Integrated Circuits using Microfluidics

2020 ◽  
Vol 7 ◽  
Author(s):  
System Administrator ◽  
Ben Andrew ◽  
Jesse McNamara ◽  
Michael Karanikolas
Keyword(s):  
Integrated Circuits ◽  
Heat Sinks ◽  
Microfluidic Channels ◽  
Negative Effects ◽  
Cooling Channels ◽  
Pin Fin ◽  
Pin Fins ◽  
Varied Size ◽  
Thermal Interfaces ◽  
Exchange Medium

The substantial increase in the transistor density of integrated circuits (ICs) in recent times has allowed considerable improvements in computing power. With increasing transistor and power density, the heat produced by modern ICs has increased significantly. This in turn has negative effects on the performance, reliability, and power consumption of the ICs. A solution to the IC’s complications caused by overheating is integrated cooling, in which cooling fluid is delivered through microchannel heat sinks on the backside of an IC. This meta-study will investigate two microfluidic cooling technologies. First, implementing varied size microfluidic channels close to the silicone substrate of the IC. Additionally, a micro-pin fin heat sink is integrated into the ICs’ fluidic microchannels. Different sized pin fins were used, to achieve a wider understanding of the application of pin fins in microfluidic cooling and compare the thermal performances of each cooling method. Integrated cooling subverts the need for suboptimal thermal interfaces and bulky heat-sinks, as well as reducing the intensity of localised hotspots commonly present in high-power electronics. Further, by locating the main heat exchange medium closer to the die of an IC, we reduce the number of thermal interfaces. This meta-study suggests that cylindrical micro-pin fin arrays with pitch longitude and latitude of 60μm and 120μm, are more thermally efficient than plain microfluidic cooling channels.  

Experimental Measurement of the Thermal Performance of a Two-Die 3D Integrated Circuit (3D IC)

2013 ◽  
Author(s):  
Leila Choobineh ◽  
Nick Vo ◽  
Trent Uehling ◽  
Ankur Jain
Keyword(s):  
Integrated Circuits ◽  
Thermal Performance ◽  
Integrated Circuit ◽  
Three Dimensional ◽  
Electrical Current ◽  
Thermal Design ◽  
3D Ic ◽  
Thermal Models ◽  
3D Ics ◽  
And Performance

Accurate measurement of the thermal performance of vertically-stacked three-dimensional integrated circuits (3D ICs) is critical for optimal design and performance. Experimental measurements also help validate thermal models for predicting the temperature field in a 3D IC. This paper presents results from thermal measurements on a two-die 3D IC. The experimental setup and procedure is described. Transient and steady-state measurements are made while heating the top die or the bottom die. Results indicate that passage of electrical current through the heaters in top/bottom die induces a measureable temperature rise. There appears to be a unique asymmetry in thermal performance between the top die and the bottom die. The top die is found to heat up faster and more than the bottom die. Results presented in this paper are expected to play a key role in validation of simulation-based and analytical thermal models for 3D ICs, and lead to a better fundamental understanding of heat transport in stacked systems. This is expected to lead to effective thermal design and characterization tools for 3D ICs.

Experimental and Numerical Investigation of Interdie Thermal Resistance in Three-Dimensional Integrated Circuits

2017 ◽  
Vol 139 (2) ◽  
Author(s):  
Leila Choobineh ◽  
Jared Jones ◽  
Ankur Jain
Keyword(s):  
Integrated Circuits ◽  
Thermal Resistance ◽  
High Speed ◽  
Three Dimensional ◽  
Heat Removal ◽  
Thermal Design ◽  
Electrical Performance ◽  
Physical Parameters ◽  
Interconnect Delay ◽  
3D Ics

Three-dimensional integrated circuits (3D ICs) attract much interest due to several advantages over traditional microelectronics design, such as electrical performance improvement and reducing interconnect delay. While the power density of 3D ICs increases because of vertical integration, the available substrate area for heat removal does not change. Thermal modeling of 3D ICs is important for improving thermal and electrical performance. Experimental investigation on the thermal measurement of 3D ICs and determination of key physical parameters in 3D ICs thermal design are curtail. One such important parameter in thermal analysis is the interdie thermal resistance between adjacent die bonded together. This paper describes an experimental method to measure the value of interdie thermal resistance between two adjacent dies in a 3D IC. The effect of heating one die on the temperature of the other die in a two-die stack is measured over a short time period using high-speed data acquisition to negate the effect of boundary conditions. Numerical simulation is performed and based on a comparison between experimental data and the numerical model, the interdie thermal resistance between the two dies is determined. A theoretical model is also developed to estimate the value of the interdie thermal resistance. Results from this paper are expected to assist in thermal design and management of 3D ICs.

Scanning Electron Microscopy in Hybrid Microelectronics

1976 ◽  
Vol 34 ◽  
pp. 456-457
Author(s):  
S. Khadpe ◽  
R. Faryniak
Keyword(s):  
Integrated Circuits ◽  
Thick Film ◽  
Integrated Circuit ◽  
Failure Modes ◽  
Three Dimensional ◽  
Circuit Components ◽  
Hybrid Microcircuit ◽  
Electrical Connections ◽  
Scanning Electron

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

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