Experimental and Numerical Investigation of Interdie Thermal Resistance in Three-Dimensional Integrated Circuits

2017 ◽  
Vol 139 (2) ◽  
Author(s):  
Leila Choobineh ◽  
Jared Jones ◽  
Ankur Jain
Keyword(s):  
Integrated Circuits ◽  
Thermal Resistance ◽  
High Speed ◽  
Three Dimensional ◽  
Heat Removal ◽  
Thermal Design ◽  
Electrical Performance ◽  
Physical Parameters ◽  
Interconnect Delay ◽  
3D Ics

Three-dimensional integrated circuits (3D ICs) attract much interest due to several advantages over traditional microelectronics design, such as electrical performance improvement and reducing interconnect delay. While the power density of 3D ICs increases because of vertical integration, the available substrate area for heat removal does not change. Thermal modeling of 3D ICs is important for improving thermal and electrical performance. Experimental investigation on the thermal measurement of 3D ICs and determination of key physical parameters in 3D ICs thermal design are curtail. One such important parameter in thermal analysis is the interdie thermal resistance between adjacent die bonded together. This paper describes an experimental method to measure the value of interdie thermal resistance between two adjacent dies in a 3D IC. The effect of heating one die on the temperature of the other die in a two-die stack is measured over a short time period using high-speed data acquisition to negate the effect of boundary conditions. Numerical simulation is performed and based on a comparison between experimental data and the numerical model, the interdie thermal resistance between the two dies is determined. A theoretical model is also developed to estimate the value of the interdie thermal resistance. Results from this paper are expected to assist in thermal design and management of 3D ICs.

Experimental Measurement of Inter-Die Thermal Resistance in a Two Die 3D IC

2016 ◽  
Author(s):  
Leila Choobineh ◽  
Ankur Jain ◽  
Jared Jones
Keyword(s):  
Thermal Resistance ◽  
Experimental Measurement ◽  
High Speed ◽  
Thermal Design ◽  
Analytical Models ◽  
Physical Parameters ◽  
3D Ic ◽  
3D Ics ◽  
High Speed Data Acquisition ◽  
High Speed Data

Thermal modeling and temperature prediction in 3D ICs are important for improving performance and reliability. A number of numerical and analytical models have been developed for thermal analysis of 3D ICs. However, there is a relative lack of experimental work to determine key physical parameters in 3D IC thermal design. One such important key parameter is the inter-die thermal resistance between adjacent die bonded together. This paper describes a novel experimental method to measure the value of inter-die thermal resistance between two die in a 3D IC. The effect of heating one die on the temperature of the other die in a two-die stack is measured over a short time period using high speed data acquisition to negate the effect of boundary conditions. Numerical simulation is performed and based on a comparison between experimental data and the numerical model, the inter-die thermal resistance between two die is determined. There is good agreement between experimental measurement and theoretically estimated value of the inter-die thermal resistance. Results from this paper are expected to assist in thermal design and management of 3D ICs.

Electrical Interconnect and Microfluidic Cooling Within 3D ICs and Silicon Interposer

2014 ◽  
Author(s):  
Hanju Oh ◽  
Yue Zhang ◽  
Li Zheng ◽  
Muhannad S. Bakir
Keyword(s):  
Integrated Circuits ◽  
Thermal Gradient ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
Heat Removal ◽  
3D Ic ◽  
Significant Challenge ◽  
3D Ics ◽  
Silicon Vias ◽  
First Time

Heat dissipation is a significant challenge for three-dimensional integrated circuits (3D IC) due to the lack of heat removal paths and increased power density. In this paper, a 3D IC system with an embedded microfluidic cooling heat sink (MFHS) is presented. In the proposed 3D IC system, high power tiers contain embedded MFHS and high-aspect ratio (23:1) through-silicon-vias (TSVs) routed through the integrated MFHS. In addition, each tier has dedicated solder-based microfluidic chip I/Os. Microfluidic cooling experiments of staggered micropin-fins with embedded TSVs are presented for the first time. Moreover, the lateral thermal gradient across a chip is analyzed with segmented heaters.

Monolithic 3D Integration of Single-Grain Si TFTs

2008 ◽  
Vol 1066 ◽  
Author(s):  
Mohammad Reza Tajari Mofrad ◽  
Ryoichi Ishihara ◽  
Jaber Derakhshandeh ◽  
Alessandro Baiano ◽  
Johan van der Cingel ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Three Dimensional ◽  
Bottom Layer ◽  
Switching Voltage ◽  
3D Integration ◽  
Monolithically Integrated ◽  
Interconnect Delay ◽  
Single Grain ◽  
Voltage Swing

ABSTRACTVertical stacking of transistors is a promising technology which can realize compact and high-speed integrated circuits (ICs) with a short interconnect delay and increased functionality. Two layers of low-temperature fabricated single-grain thin-film transistors (SG TFTs) have been monolithically integrated. NMOS mobilities are 565 and 393 cm2/Vs and pMOS mobilities are 159 and 141 cm2/Vs, for the top and bottom layers respectively. A three-dimensional (3D) inverter has also been fabricated, with one transistor on the bottom layer and the other on the top layer. The inverters showed an output voltage swing of 0 to 5 V with a switching voltage of around 2 V.

Experimental Measurement of the Thermal Performance of a Two-Die 3D Integrated Circuit (3D IC)

2013 ◽  
Author(s):  
Leila Choobineh ◽  
Nick Vo ◽  
Trent Uehling ◽  
Ankur Jain
Keyword(s):  
Integrated Circuits ◽  
Thermal Performance ◽  
Integrated Circuit ◽  
Three Dimensional ◽  
Electrical Current ◽  
Thermal Design ◽  
3D Ic ◽  
Thermal Models ◽  
3D Ics ◽  
And Performance

Accurate measurement of the thermal performance of vertically-stacked three-dimensional integrated circuits (3D ICs) is critical for optimal design and performance. Experimental measurements also help validate thermal models for predicting the temperature field in a 3D IC. This paper presents results from thermal measurements on a two-die 3D IC. The experimental setup and procedure is described. Transient and steady-state measurements are made while heating the top die or the bottom die. Results indicate that passage of electrical current through the heaters in top/bottom die induces a measureable temperature rise. There appears to be a unique asymmetry in thermal performance between the top die and the bottom die. The top die is found to heat up faster and more than the bottom die. Results presented in this paper are expected to play a key role in validation of simulation-based and analytical thermal models for 3D ICs, and lead to a better fundamental understanding of heat transport in stacked systems. This is expected to lead to effective thermal design and characterization tools for 3D ICs.

Microprocessor Silicon Die Temperature Prediction by Simplified Boundary Conditions

2015 ◽  
Author(s):  
Koji Nishi ◽  
Tomoyuki Hatakeyama ◽  
Shinji Nakagawa ◽  
Masaru Ishizuka
Keyword(s):  
Heat Transfer ◽  
Heat Conduction ◽  
Boundary Conditions ◽  
Thermal Resistance ◽  
Hot Spot ◽  
Three Dimensional ◽  
Thermal Design ◽  
Target Temperature ◽  
One Dimensional ◽  
Thermal Network

The thermal network method has a long history with thermal design of electronic equipment. In particular, a one-dimensional thermal network is useful to know the temperature and heat transfer rate along each heat transfer path. It also saves computation time and/or computation resources to obtain target temperature. However, unlike three-dimensional thermal simulation with fine pitch grids and a three-dimensional thermal network with sufficient numbers of nodes, a traditional one-dimensional thermal network cannot predict the temperature of a microprocessor silicon die hot spot with sufficient accuracy in a three-dimensional domain analysis. Therefore, this paper introduces a one-dimensional thermal network with average temperature nodes. Thermal resistance values need to be obtained to calculate target temperature in a thermal network. For this purpose, thermal resistance calculation methodology with simplified boundary conditions, which calculates thermal resistance values from an analytical solution, is also introduced in this paper. The effectiveness of the methodology is explored with a simple model of the microprocessor system. The calculated result by the methodology is compared to a three-dimensional heat conduction simulation result. It is found that the introduced technique matches the three-dimensional heat conduction simulation result well.

Development of Backside Buried Metal Layer Technology for 3D-ICs

2019 ◽  
Vol 2019 (1) ◽  
pp. 000268-000273
Author(s):  
Naoya Watanabe ◽  
Yuuki Araga ◽  
Haruo Shimamoto ◽  
Katsuya Kikuchi ◽  
Makoto Nagata
Keyword(s):  
Integrated Circuits ◽  
Metal Layer ◽  
Three Dimensional ◽  
Chip Thickness ◽  
Power Delivery ◽  
Silicon Structure ◽  
Metal Insulator ◽  
3D Ics ◽  
Power Delivery Network ◽  
Global Power

Abstract In this study, we developed backside buried metal (BBM) layer technology for three-dimensional integrated circuits (3D-ICs). In this technology, a BBM layer for global power routing is introduced in the large vacant area on the backside of each chip and is parallelly connected with the frontside routing of the chip. The resistances of the power supply (VDD) and ground (VSS) lines consequently decrease. In addition, the BBM structure acts as a decoupling capacitor because it is buried in the Si substrate and has metal–insulator–silicon structure. Therefore, the impedance of power delivery network can be reduced by introducing the BBM layer. The fabrication process of the BBM layer for 3D-ICs was simple and compatible with the via-last through-silicon via (TSV) process. With this process, it was possible to fabricate the BBM layer consisting of electroplated Cu (thickness: approximately 10 μm) buried in the backside of the CMOS chip (thickness: 43 μm), which was connected with the frontside routing of the chip using 9 μm-diameter TSVs.

Barrier Properties of Electroless Ni-B UBM for Solder Joining

2015 ◽  
Vol 2015 (1) ◽  
pp. 000862-000867
Author(s):  
Masaru Morita ◽  
Toshiya Akamatsu ◽  
Nobuhiro Imaizumi ◽  
Seiki Sakuyama
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Solid Phase ◽  
Barrier Properties ◽  
Electrode Structure ◽  
Phase Diffusion ◽  
3D Ics ◽  
The Difference ◽  
Electroless Ni ◽  
Plating Layer

As demands accelerate for high density, high speed transmission and low power integrated circuits, 3D-ICs with through-silicon via (TSV) is pursued. In the structure of 3D-ICs, the first die is attached to the second die with micro bump, and the second die is attached to the circuit substrate with a C4 solder bump. The electrode structure of the second die is Cu/Ni UBM. The stress of the Ni-B layer is less than that of the Ni-P layer, and the Ni-B layer can suppress stress and die warpage. The purposes of our study are to clarify the difference in the barrier properties of the Ni-B UBM and Ni-P under bump metal (UBM) and the relevance of the barrier properties of Ni UBM and intermetallic compound (IMC) growth. It was found that an electroless Ni-B plating layer is superior to a Ni-P plating layer for UBM in liquid phase diffusion and in solid phase diffusion, and that a segregated B layer is formed under the IMC layer of a Ni-B land due to reflow soldering. It was estimated that this B layer plays the role of being a barrier layer for solder diffusion.

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