PLL soft functional failure analysis in advanced logic product using fault based analogue simulation and soft defect localization

2008 ◽  
Vol 48 (8-9) ◽  
pp. 1349-1353 ◽  
Author(s):  
Liming Gao ◽  
Christian Burmer
Keyword(s):  
Failure Analysis ◽  
Functional Failure ◽  
Analogue Simulation ◽  
Defect Localization

Advanced CMOS Device Fault Isolation Using Frequency Mapping on Passive Structures

2013 ◽  
Author(s):  
S.H. Goh ◽  
B.L. Yeoh ◽  
G.F. You ◽  
W.H. Hung ◽  
Jeffrey Lam ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Fault Isolation ◽  
Device Failure ◽  
Functional Failure ◽  
Technology Node ◽  
Defect Localization ◽  
Emission Microscopy ◽  
Scan Chains

Abstract Backside frequency mapping on modulating active in transistors is well established for defect localization on broken scan chains. Recent experiments have proven the existence of frequency signals from passive structures modulations. In this paper, we demonstrate the effectiveness of this technique on a 65 nm technology node device failure. A resistive leaky path leading to a functional failure which, otherwise cannot be isolated using dynamic emission microscopy, is localized in this work to guide follow on failure analysis.

Accurate Defect Localization of Stacked Die Devices by Lock-in Thermography

2018 ◽  
Author(s):  
Ke-Ying Lin ◽  
Chih-Yi Tang ◽  
Yu Chi Wang
Keyword(s):  
Failure Analysis ◽  
Defect Modes ◽  
Defect Localization ◽  
Lock In

Abstract The paper demonstrates the moving of lock-in thermography (LIT) spot location by adjusting the lock-in frequency from low to high. Accurate defect localization in stacked-die devices was decided by the fixed LIT spot location after the lock-in frequency was higher than a specific value depending on the depth of the defect in the IC. Physical failure analysis was performed based on LIT results, which provided clear physical defect modes of the stacked-die devices.

Test Circuit Conditioning for Soft Defect Localization

2014 ◽  
Author(s):  
Kristopher D. Staller ◽  
Corey Goodrich
Keyword(s):  
Laser Beam ◽  
Failure Analysis ◽  
Signal Frequency ◽  
Dynamic Failure ◽  
The Third ◽  
Analysis Technique ◽  
Test Circuit ◽  
Defect Localization ◽  
Manual Input ◽  
Fast Dynamic

Abstract Soft Defect Localization (SDL) is a dynamic laser-based failure analysis technique that can detect circuit upsets (or cause a malfunctioning circuit to recover) by generation of localized heat or photons from a rastered laser beam. SDL is the third and seldom used method on the LSM tool. Most failure analysis LSM sessions use the endo-thermic mode (TIVA, XIVA, OBIRCH), followed by the photo-injection mode (LIVA) to isolate most of their failures. SDL is seldom used or attempted, unless there is a unique and obvious failure mode that can benefit from the application. Many failure analysts, with a creative approach to the analysis, can employ SDL. They will benefit by rapidly finding the location of the failure mechanism and forgoing weeks of nodal probing and isolation. This paper will cover circuit signal conditioning to allow for fast dynamic failure isolation using an LSM for laser stimulation. Discussions of several cases will demonstrate how the laser can be employed for triggering across a pass/fail boundary as defined by voltage levels, supply currents, signal frequency, or digital flags. A technique for manual input of the LSM trigger is also discussed.

Application of AFP in Resolving Systematic Issue in Wafer Fabrication

2013 ◽  
Author(s):  
Hui Peng Ng ◽  
Ghim Boon Ang ◽  
Chang Qing Chen ◽  
Alfred Quah ◽  
Angela Teo ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Failure Mechanisms ◽  
Critical Role ◽  
Electrical Characterization ◽  
Process Technology ◽  
Atomic Force ◽  
Defect Localization ◽  
Non Volatile Memory ◽  
Visual Failure

Abstract With the evolution of advanced process technology, failure analysis is becoming much more challenging and difficult particularly with an increase in more erratic defect types arising from non-visual failure mechanisms. Conventional FA techniques work well in failure analysis on defectively related issue. However, for soft defect localization such as S/D leakage or short due to design related, it may not be simple to identify it. AFP and its applications have been successfully engaged to overcome such shortcoming, In this paper, two case studies on systematic issues due to soft failures were discussed to illustrate the AFP critical role in current failure analysis field on these areas. In other words, these two case studies will demonstrate how Atomic Force Probing combined with Scanning Capacitance Microscopy were used to characterize failing transistors in non-volatile memory, identify possible failure mechanisms and enable device/ process engineers to make adjustment on process based on the electrical characterization result. [1]

Laser Voltage Imaging: A New Perspective of Laser Voltage Probing

2010 ◽  
Author(s):  
Yin S. Ng ◽  
Ted Lundquist ◽  
Dmitry Skvortsov ◽  
Joy Liao ◽  
Steven Kasapi ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Functional Failure ◽  
Voltage Imaging ◽  
Laser Probing ◽  
New Perspective

Abstract Laser Voltage Imaging (LVI) is a new application developed from Laser Voltage Probing (LVP). Most LVP applications have focused on design debug or design characterization, and are seldom used for global functional failure analysis. LVI enables the failure analysis engineer to utilize laser probing techniques in the failure analysis realm. In this paper, we present LVI as an emerging FA technique. We will discuss setting up an LVI acquisition and present its current challenges. Finally, we will present an LVI application in the form of a case study.

Identification of Human Errors During Early Design Stage Functional Failure Analysis

2018 ◽  
Author(s):  
Lukman Irshad ◽  
Salman Ahmed ◽  
Onan Demirel ◽  
Irem Y. Tumer
Keyword(s):  
Failure Analysis ◽  
Human Error ◽  
System Level ◽  
Design Stage ◽  
Human Factors Engineering ◽  
Human Errors ◽  
Functional Failure ◽  
Early Design ◽  
Early Design Stage ◽  
Early Design Stages

Detection of potential failures and human error and their propagation over time at an early design stage will help prevent system failures and adverse accidents. Hence, there is a need for a failure analysis technique that will assess potential functional/component failures, human errors, and how they propagate to affect the system overall. Prior work has introduced FFIP (Functional Failure Identification and Propagation), which considers both human error and mechanical failures and their propagation at a system level at early design stages. However, it fails to consider the specific human actions (expected or unexpected) that contributed towards the human error. In this paper, we propose a method to expand FFIP to include human action/error propagation during failure analysis so a designer can address the human errors using human factors engineering principals at early design stages. To explore the capabilities of the proposed method, it is applied to a hold-up tank example and the results are coupled with Digital Human Modeling to demonstrate how designers can use these tools to make better design decisions before any design commitments are made.

Computational Functional Failure Analysis to Identify Human Errors During Early Design Stages

2019 ◽  
Vol 19 (3) ◽  
Author(s):  
Lukman Irshad ◽  
Salman Ahmed ◽  
H. Onan Demirel ◽  
Irem Y. Tumer
Keyword(s):  
Failure Analysis ◽  
Human Error ◽  
Human Action ◽  
System Level ◽  
Design Stage ◽  
Human Factors Engineering ◽  
Human Errors ◽  
Functional Failure ◽  
Early Design ◽  
Early Design Stages

Detection of potential failures and human error and their propagation over time at an early design stage will help prevent system failures and adverse accidents. Hence, there is a need for a failure analysis technique that will assess potential functional/component failures, human errors, and how they propagate to affect the system overall. Prior work has introduced functional failure identification and propagation (FFIP), which considers both human error and mechanical failures and their propagation at a system level at early design stages. However, it fails to consider the specific human actions (expected or unexpected) that contributed toward the human error. In this paper, we propose a method to expand FFIP to include human action/error propagation during failure analysis so a designer can address the human errors using human factors engineering principals at early design stages. The capabilities of the proposed method is presented via a hold-up tank example, and the results are coupled with digital human modeling to demonstrate how designers can use these tools to make better design decisions before any design commitments are made.

The Application of Novel Failure Analysis Techniques and Defect Modeling in Eliminating Short Poly End-Cap Problem in Submicron CMOS Devices

1996 ◽  
Author(s):  
Y.E. Hong ◽  
M.T.T. We
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Leakage Current ◽  
Packing Density ◽  
Process Change ◽  
Defect Modeling ◽  
Functional Failure ◽  
Analysis Techniques ◽  
Post Process ◽  
First Time

Abstract As transistor dimension shrinks down below submicron to cater for higher speed and higher packing density, it is very important to characterize the shrinkage carefully to avoid unwanted parametric problems. Leakage current across short poly end-cap is a new failure mechanism that falls in this category and was for the first time, uncovered in submicron multilayered CMOS devices. This mechanism was responsible for a systematic yield problem; identified as the 'centre wafer striping' functional failure problem. This paper presents the advanced failure analysis techniques and defect modeling used to narrow down and identify this new mechanism. Post process change by loosening the marginal poly end-cap criteria eliminated the problem completely.

Product Debug: Speed Problem Related to Unexpected RC Delay

2010 ◽  
Author(s):  
J.G. van Hassel ◽  
F. Zachariasse
Keyword(s):  
Failure Analysis ◽  
Failure Mechanisms ◽  
Audio Signal ◽  
New Product ◽  
Analysis Method ◽  
Standard Analysis ◽  
Time Resolved ◽  
Defect Localization ◽  
Rc Delay ◽  
Comprehensive Study

Abstract In new product designs increasing effort is needed to observe and prove failure mechanisms or process marginalities. For advanced failure analysis Soft Defect Localization (SDL) [1] and Time Resolved Emission (TRE) [2,3] have now become a standard analysis method. Both techniques require a close co-operation between designers and analysts. In this paper we will discuss a comprehensive study to find the mechanism behind a speed problem in the digital part of an audio signal processor. The additional delay was related to unwanted routing through poly-silicide in timing critical circuitry.

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