Accurate Defect Localization of Stacked Die Devices by Lock-in Thermography

2018 ◽  
Author(s):  
Ke-Ying Lin ◽  
Chih-Yi Tang ◽  
Yu Chi Wang
Keyword(s):  
Failure Analysis ◽  
Defect Modes ◽  
Defect Localization ◽  
Lock In

Abstract The paper demonstrates the moving of lock-in thermography (LIT) spot location by adjusting the lock-in frequency from low to high. Accurate defect localization in stacked-die devices was decided by the fixed LIT spot location after the lock-in frequency was higher than a specific value depending on the depth of the defect in the IC. Physical failure analysis was performed based on LIT results, which provided clear physical defect modes of the stacked-die devices.

Test Circuit Conditioning for Soft Defect Localization

2014 ◽  
Author(s):  
Kristopher D. Staller ◽  
Corey Goodrich
Keyword(s):  
Laser Beam ◽  
Failure Analysis ◽  
Signal Frequency ◽  
Dynamic Failure ◽  
The Third ◽  
Analysis Technique ◽  
Test Circuit ◽  
Defect Localization ◽  
Manual Input ◽  
Fast Dynamic

Abstract Soft Defect Localization (SDL) is a dynamic laser-based failure analysis technique that can detect circuit upsets (or cause a malfunctioning circuit to recover) by generation of localized heat or photons from a rastered laser beam. SDL is the third and seldom used method on the LSM tool. Most failure analysis LSM sessions use the endo-thermic mode (TIVA, XIVA, OBIRCH), followed by the photo-injection mode (LIVA) to isolate most of their failures. SDL is seldom used or attempted, unless there is a unique and obvious failure mode that can benefit from the application. Many failure analysts, with a creative approach to the analysis, can employ SDL. They will benefit by rapidly finding the location of the failure mechanism and forgoing weeks of nodal probing and isolation. This paper will cover circuit signal conditioning to allow for fast dynamic failure isolation using an LSM for laser stimulation. Discussions of several cases will demonstrate how the laser can be employed for triggering across a pass/fail boundary as defined by voltage levels, supply currents, signal frequency, or digital flags. A technique for manual input of the LSM trigger is also discussed.

Application of AFP in Resolving Systematic Issue in Wafer Fabrication

2013 ◽  
Author(s):  
Hui Peng Ng ◽  
Ghim Boon Ang ◽  
Chang Qing Chen ◽  
Alfred Quah ◽  
Angela Teo ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Failure Mechanisms ◽  
Critical Role ◽  
Electrical Characterization ◽  
Process Technology ◽  
Atomic Force ◽  
Defect Localization ◽  
Non Volatile Memory ◽  
Visual Failure

Abstract With the evolution of advanced process technology, failure analysis is becoming much more challenging and difficult particularly with an increase in more erratic defect types arising from non-visual failure mechanisms. Conventional FA techniques work well in failure analysis on defectively related issue. However, for soft defect localization such as S/D leakage or short due to design related, it may not be simple to identify it. AFP and its applications have been successfully engaged to overcome such shortcoming, In this paper, two case studies on systematic issues due to soft failures were discussed to illustrate the AFP critical role in current failure analysis field on these areas. In other words, these two case studies will demonstrate how Atomic Force Probing combined with Scanning Capacitance Microscopy were used to characterize failing transistors in non-volatile memory, identify possible failure mechanisms and enable device/ process engineers to make adjustment on process based on the electrical characterization result. [1]

Failure Analysis Strategies for Multistacked Memory Devices with TSV Interconnects

2015 ◽  
Author(s):  
Frank Altmann ◽  
Christian Grosse ◽  
Falk Naumann ◽  
Jens Beyersdorfer ◽  
Tony Veches
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Memory Devices ◽  
Metallographic Cross Section ◽  
Electron Beam Induced Current ◽  
Thermal Simulations ◽  
Lock In ◽  
Non Destructive

Abstract In this paper we will demonstrate new approaches for failure analysis of memory devices with multiple stacked dies and TSV interconnects. Therefore, TSV specific failure modes are studied on daisy chain test samples. Two analysis flows for defect localization implementing Electron Beam Induced Current (EBAC) imaging and Lock-in-Thermography (LIT) as well as adapted Focused Ion Beam (FIB) preparation and defect characterization by electron microscopy will be discussed. The most challenging failure mode is an electrical short at the TSV sidewall isolation with sub-micrometer dimensions. It is shown that the leakage path to a certain TSV within the stack can firstly be located by applying LIT to a metallographic cross section and secondly pinpointing by FIB/SEM cross-sectioning. In order to evaluate the potential of non-destructive determination of the lateral defect position, as well as the defect depth from only one LIT measurement, 2D thermal simulations of TSV stacks with artificial leakages are performed calculating the phase shift values per die level.

scholarly journals Infrared Thermography applied to power electron devices investigation

2015 ◽  
Vol 28 (2) ◽  
pp. 205-212 ◽  
Author(s):  
Giovanni Breglio ◽  
Andrea Irace ◽  
Luca Maresca ◽  
Michele Riccio ◽  
Gianpaolo Romano ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Infrared Thermography ◽  
Semiconductor Devices ◽  
Electronic Devices ◽  
Experimental Characterization ◽  
Ir Thermography ◽  
Power Semiconductor ◽  
Power Semiconductor Devices ◽  
Electron Devices ◽  
Lock In

The aim of this paper is to give a presentation of the principal applications of Infrared Thermography for analysis and testing of electrondevices. Even though experimental characterization could be carried out on almost any electronic devices and circuits, here IR Thermography for investigation of power semiconductor devices is presented. Different examples of functional and failure analysis in both transient and lock-in modes will be reported.

Fault Isolation of Metal-Insulator-Metal (MiM) Capacitor Failures by Lock-in Thermography (LIT)

2020 ◽  
Author(s):  
Ke-Ying Lin ◽  
Pei-Fen Lue ◽  
Jayce Liu ◽  
Paul Kenneth Ang
Keyword(s):  
Fault Isolation ◽  
Phase Image ◽  
Metal Insulator ◽  
Amplitude Image ◽  
Metal Insulator Metal ◽  
Defect Localization ◽  
Lock In

Abstract The paper demonstrates accurate fault isolation information of metal-insulator-metal (MiM) capacitor failures by lock-in thermograph (LIT). In this study, a phase image spot location at a lock-in frequency larger than 5 Hz gives more accurate defect localization than an LIT amplitude image or OBIRCH to determine the next FA steps.

Localization of Hotspots from Lock-in Thermography Images for Failure Analysis

2021 ◽  
Author(s):  
Rui Zhen Tan ◽  
Neelakantam Venkatarayalu ◽  
Zhongqiang Ding ◽  
Indriyati Atmosukarto ◽  
A. B. Premkumar ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Lock In

scholarly journals 3D Defect Localization on Exothermic Faults within Multi-Layered Structures Using Lock-In Thermography: An Experimental and Numerical Approach

Sensors ◽  
2017 ◽  
Vol 17 (10) ◽  
pp. 2331
Author(s):  
Ji Bae ◽  
Kye-Sung Lee ◽  
Hwan Hur ◽  
Ki-Hwan Nam ◽  
Suk-Ju Hong ◽  
...  
Keyword(s):  
Numerical Approach ◽  
Layered Structures ◽  
Defect Localization ◽  
Lock In
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