Application of AFP in Resolving Systematic Issue in Wafer Fabrication

2013 ◽  
Author(s):  
Hui Peng Ng ◽  
Ghim Boon Ang ◽  
Chang Qing Chen ◽  
Alfred Quah ◽  
Angela Teo ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Failure Mechanisms ◽  
Critical Role ◽  
Electrical Characterization ◽  
Process Technology ◽  
Atomic Force ◽  
Defect Localization ◽  
Non Volatile Memory ◽  
Visual Failure

Abstract With the evolution of advanced process technology, failure analysis is becoming much more challenging and difficult particularly with an increase in more erratic defect types arising from non-visual failure mechanisms. Conventional FA techniques work well in failure analysis on defectively related issue. However, for soft defect localization such as S/D leakage or short due to design related, it may not be simple to identify it. AFP and its applications have been successfully engaged to overcome such shortcoming, In this paper, two case studies on systematic issues due to soft failures were discussed to illustrate the AFP critical role in current failure analysis field on these areas. In other words, these two case studies will demonstrate how Atomic Force Probing combined with Scanning Capacitance Microscopy were used to characterize failing transistors in non-volatile memory, identify possible failure mechanisms and enable device/ process engineers to make adjustment on process based on the electrical characterization result. [1]

Case Studies in Atomic Force Probe Analysis

2006 ◽  
Author(s):  
Randal Mulder ◽  
Sam Subramanian ◽  
Tony Chrastecky
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Light Emission ◽  
Electrical Characterization ◽  
Logic Circuits ◽  
Contrast Imaging ◽  
Atomic Force ◽  
Measuring Surface ◽  
Analysis Environment

Abstract The use of atomic force probe (AFP) analysis in the analysis of semiconductor devices is expanding from its initial purpose of solely characterizing CMOS transistors at the contact level with a parametric analyzer. Other uses found for the AFP include the full electrical characterization of failing SRAM bit cells, current contrast imaging of SOI transistors, measuring surface roughness, the probing of metallization layers to measure leakages, and use with other tools, such as light emission, to quickly localize and identify defects in logic circuits. This paper presents several case studies in regards to these activities and their results. These case studies demonstrate the versatility of the AFP. The needs and demands of the failure analysis environment have quickly expanded its use. These expanded capabilities make the AFP more valuable for the failure analysis community.

Coupling C-AFM with Nanoprobing Technique for Further Junction Leakage Analysis

2006 ◽  
Author(s):  
Cha-Ming Shen ◽  
Tsan-Chen Chuang ◽  
Chen-May Huang ◽  
Shi-Chen Lin ◽  
Jie-Fei Chang
Keyword(s):  
Failure Analysis ◽  
Atomic Force Microscope ◽  
Failure Modes ◽  
Electrical Characteristic ◽  
Failure Mechanisms ◽  
Gate Leakage ◽  
Process Technology ◽  
Analysis Techniques ◽  
Atomic Force ◽  
Or Gate

Abstract With the evolution of advanced process technology, failure analysis has become more and more difficult because more defects are of the non-visual type (very tiny or even invisible defects) from new failure mechanisms. In this article, a novel and effective methodology which couples the conductive atomic force microscope (C-AFM) with nano-probing technique is proposed to reveal some particular failure modes which were not observable and difficult to identify with traditional physical failure analysis techniques. The capability of coupling C-AFM with nano-probing technique is used to distinguish cases which suffer general junction leakage or gate leakage from those that form the fake junction leakage or gate leakage cases. C-AFM can detect the abnormal contacts quickly, and nano-probing could provide the precise electrical characteristic further. Then, combining these variant measuring results, the favorable tactics can be adopted to deal with different states.

The Electrical Characterization and Physical Failure Analysis for Transistor Gate Leakage

2006 ◽  
Author(s):  
Tsung-Te Li ◽  
Chao-Chi Wu ◽  
Jung-Hsiang Chuang ◽  
Jon C. Lee
Keyword(s):  
Failure Analysis ◽  
Electrical Characterization ◽  
Physical Analysis ◽  
Gate Leakage ◽  
Force Microscopy ◽  
Atomic Force ◽  
Transmission Electron ◽  
Voltage Stress ◽  
Leakage Site

Abstract This article describes the electrical and physical analysis of gate leakage in nanometer transistors using conducting atomic force microscopy (C-AFM), nano-probing, transmission electron microscopy (TEM), and chemical decoration on simulated overstressed devices. A failure analysis case study involving a soft single bit failure is detailed. Following the nano-probing analysis, TEM cross sectioning of this failing device was performed. A voltage bias was applied to exaggerate the gate leakage site. Following this deliberate voltage overstress, a solution of boiling 10%wt KOH was used to etch decorate the gate leakage site followed by SEM inspection. Different transistor leakage behaviors can be identified with nano-probing measurements and then compared with simulation data for increased confidence in the failure analysis result. Nano-probing can be used to apply voltage stress on a transistor or a leakage path to worsen the weak point and then observe the leakage site easier.

Combine Micro-Probing and OBIRCH to Catch Non-Recognizable Fault in RF and Mixed-Mode Integrated Circuits

2007 ◽  
Author(s):  
Cha-Ming Shen ◽  
Yen-Long Chang ◽  
Lian-Fon Wen ◽  
Tan-Chen Chuang ◽  
Shi-Chen Lin ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Radio Frequency ◽  
Failure Analysis ◽  
Case Studies ◽  
Mixed Mode ◽  
Failure Mechanisms ◽  
Deep Submicron ◽  
Digital Logic ◽  
Successful Approach ◽  
Cmos Processes

Abstract Highly-integrated radio frequency and mixed-mode devices that are manufactured in deep-submicron or more advanced CMOS processes are becoming more complex to analyze. The increased complexity presents us with many eccentric failure mechanisms that are uniquely different from traditional failure mechanisms found during failure analysis on digital logic applications. This paper presents a novel methodology to overcome the difficulties and discusses two case studies which demonstrate the application of the methodology. Through the case studies, the methodology was proven to be a successful approach. It is also proved how this methodology would work for such non-recognizable failures.

Product Debug: Speed Problem Related to Unexpected RC Delay

2010 ◽  
Author(s):  
J.G. van Hassel ◽  
F. Zachariasse
Keyword(s):  
Failure Analysis ◽  
Failure Mechanisms ◽  
Audio Signal ◽  
New Product ◽  
Analysis Method ◽  
Standard Analysis ◽  
Time Resolved ◽  
Defect Localization ◽  
Rc Delay ◽  
Comprehensive Study

Abstract In new product designs increasing effort is needed to observe and prove failure mechanisms or process marginalities. For advanced failure analysis Soft Defect Localization (SDL) [1] and Time Resolved Emission (TRE) [2,3] have now become a standard analysis method. Both techniques require a close co-operation between designers and analysts. In this paper we will discuss a comprehensive study to find the mechanism behind a speed problem in the digital part of an audio signal processor. The additional delay was related to unwanted routing through poly-silicide in timing critical circuitry.

Improved SRAM 6T Bit Cell Failure Analysis Using MCSpice Bit Cell Defect Modeling

2003 ◽  
Author(s):  
Randal Mulder ◽  
Sam Subramanian ◽  
Ed Widener ◽  
Tony Chrastecky
Keyword(s):  
Failure Analysis ◽  
Success Rate ◽  
Case Studies ◽  
Failure Mode ◽  
Failure Mechanisms ◽  
Physical Analysis ◽  
Certification Programs ◽  
Current Voltage ◽  
Electrical Analysis ◽  
Cell Defect

Abstract Single bit failures are the dominant failure mode for SRAM 6T bit cell memory devices. The analysis of failing single bits is aided by the fact that the mechanism is localized to the failing 6T bit cell. After electrically analyzing numerous failing bits, it was observed that failing bit cells were consistently producing specific electrical signatures (current-voltage curves). To help identify subtle bit cell failure mechanisms, this paper discusses an MCSpice program which was needed to simulate a 6T SRAM bit cell and the electrical analysis. It presents four case studies that show how MCSpice modeling of defective 6T SRAM bit cells was successfully used to identify subtle defect types (opens or shorts) and locations within the failing cell. The use of an MCSpice simulation and the appropriate physical analysis of defective bit cells resulted in a >90% success rate for finding failure mechanisms on yield and process certification programs.

Case Studies of the Use of Image Processing in Metrology and Failure Analysis

2005 ◽  
Author(s):  
Kartik Ramanujachar
Keyword(s):  
Image Processing ◽  
Failure Analysis ◽  
Case Studies ◽  
Nearest Neighbor ◽  
Image Data ◽  
Cumulative Distribution ◽  
Information Theoretic ◽  
Atomic Force ◽  
Processing Techniques

Abstract This paper describes the use of image processing techniques in metrology and failure analysis with the help of three case studies. The first study concerns a technique that significantly automates the process and hence enables both a rapid and accurate extraction of cumulative distribution function for transistor CD through the use of edge detection and quantification of image intensities. The second study is about utilizing a cross correlation algorithm and an appropriately chosen sample and image to estimate the "on image" spatial resolution of an scanning electron microscope. The last case study uses image data acquired with an atomic force microscope. The paper describes how information theoretic concepts like entropy and mutual information combined with image segmentation and nearest neighbor extraction can be used to isolate those regions of the AFM scan that can potentially benefit from further analysis.

Two Unique Case Studies Performed With Photoemission Microscopy (PEM)

1996 ◽  
Author(s):  
G.F. Shade
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Case Studies ◽  
Current Flow ◽  
Failure Mechanisms ◽  
Analysis Time ◽  
Unique Case ◽  
Qualitative Evidence ◽  
Leakage Path

Abstract Two cases are presented where photoemission microscopy (PEM) quickly reduced the analysis time by providing qualitative evidence of the suspected failure mechanisms. In both cases, the failures were delaying product shipments and the PEM technique was a "last hope" approach where other proposals were either not successful, or were not available to the analysts. In case one, package residue caused a leakage path that was located and confirmed by PEM. The second case required the use of PEM to observe uniformity of current flow within a polysilicon region. This second analysis provided absolute evidence that the current flow was nonuniform which supported the suspected failure mechanism. It is believed that this is the first reported observation of these two emission mechanisms during a failure analysis.

Laser Voltage Imaging and Its Derivatives—Efficient Techniques to Address Defect on 28 nm Technology

2013 ◽  
Author(s):  
Thierry Parrassin ◽  
Guillaume Celi ◽  
Sylvain Dudit ◽  
Michel Vallet ◽  
Antoine Reverdy ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Second Harmonic ◽  
Advanced Technology ◽  
Added Value ◽  
Harmonic Detection ◽  
Localization Technique ◽  
Voltage Imaging ◽  
Advanced Technologies ◽  
Defect Localization

Abstract The Laser Voltage Imaging (LVI) technique, introduced in 2007 [1][2], has been demonstrated as a successful defect localization technique to address problems on advanced technologies. In this paper, several 28nm case studies are described on which the LVI technique and its derivatives provide a real added value to the defect localization part of the Failure Analysis flow. We will show that LVI images can be used as a great reference to improve the CAD alignment overlay accuracy which is critical for advanced technology debug. Then, we will introduce several case studies on 28nm technology on which Thermal Frequency Imaging (TFI) and Second Harmonic Detection (two LVI derivative techniques) allow efficient defect localization.

MEMS Failure Analysis In Wafer Fabrication

2016 ◽  
Author(s):  
Hui Peng Ng ◽  
Angela Teo ◽  
Ghim Boon Ang ◽  
Alfred Quah ◽  
N. Dayanand ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Data Interpretation ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Auger Analysis ◽  
Root Cause ◽  
Defect Site ◽  
Defect Localization ◽  
Cmos Chip

Abstract This paper discussed on how the importance of failure analysis to identify the root cause and mechanism that resulted in the MEMS failure. The defect seen was either directly on the MEMS caps or the CMOS integrated chip in wafer fabrication. Two case studies were highlighted in the discussion to demonstrate how the FA procedures that the analysts had adopted in order to narrow down to the defect site successfully on MEMS cap as well as on CMOS chip on MEMS package units. Besides the use of electrical fault isolation tool/technique such as TIVA for defect localization, a new physical deprocessing approach based on the cutting method was performed on the MEMS package unit in order to separate the MEMS from the Si Cap. This approach would definitely help to prevent the introduction of particles and artifacts during the PFA that could mislead the FA analyst into wrong data interpretation. Other FA tool such as SEM inspection to observe the physical defect and Auger analysis to identify the elements in the defect during the course of analysis were also documented in this paper.

Sign in / Sign up

Export Citation Format

Share Document