scholarly journals Analysis and Design of Subthreshold Leakage Power-aware Ripple Carry Adder at Circuit-level Using 90nm Technology

2015 ◽  
Vol 48 ◽  
pp. 660-665 ◽  
Author(s):  
G. Amuthavalli ◽  
R. Gunasundari
Keyword(s):  
Leakage Power ◽  
Analysis And Design ◽  
Ripple Carry Adder ◽  
Subthreshold Leakage

Full-Chip Subthreshold Leakage Power Prediction and Reduction Techniques for Sub-0.18-<tex>$mu$</tex>m CMOS

2004 ◽  
Vol 39 (3) ◽  
pp. 501-510 ◽  
Author(s):  
S. Narendra ◽  
V. De ◽  
S. Borkar ◽  
D.A. Antoniadis ◽  
A.P. Chandrakasan
Keyword(s):  
Leakage Power ◽  
Power Prediction ◽  
Reduction Techniques ◽  
Subthreshold Leakage

scholarly journals Design of Low Leakage Arithmetic Logic circuit Using Efficient Power Gating Schemes

2019 ◽  
Vol 7 (3) ◽  
pp. 11-18
Author(s):  
Yogesh Kulshethra ◽  
Manish Kule
Keyword(s):  
Leakage Current ◽  
Supply Voltage ◽  
Leakage Power ◽  
Power Gating ◽  
Design Constraint ◽  
Analysis And Design ◽  
Complex Arithmetic ◽  
Look Ahead ◽  
Simulation Results ◽  
Gating Scheme

As technology scales towards nanometer regime the leakage power consumption emerging as a major design constraint for the analysis and design of complex arithmetic logic circuits. In this paper, comparative analysis of standby leakage current and sleep to active mode transition leakage current has been done. An innovative power gating approaches is also analyzed which targets maximum reduction of major leakage current. To analyze we introduce the stacking power gating scheme, we implemented this scheme on carry look ahead adder circuit and then simulation has been done using stacking power gating scheme with 45nm technology parameters. The simulation results by using this scheme in BPTM 45nm technology with supply voltage of 0.9V at room temperature shows that leakage reduction can be improved by 47.14% as on comparison with single transistor gating scheme on comparing with conventional scheme Also, another novel approach has been analyzed with diode based stacking power gating scheme for further reduction in leakage power. The simulation results depicts that the analyzed design leads to efficient carry look ahead adder circuit in terms of leakage power, active power and delay.

scholarly journals Design of CNTFET Based Domino Wide OR Gates Using Dual Chirality for Reducing Subthreshold Leakage Current

2021 ◽  
Author(s):  
Vijay Kumar Magraiya ◽  
Tarun Kumar Gupta ◽  
Bharat Garg
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
Leakage Current ◽  
Field Effect Transistors ◽  
Leakage Power ◽  
High Input ◽  
Low Input ◽  
Prime Concern ◽  
Subthreshold Leakage ◽  
Domino Circuits

Abstract The leakage current is prime concern in the modern portable battery operated device. However, various techniques are presented and performance is evaluated using MOSFET and FinFET devices. To further reduce leakage current for improved battery backup in portable devices, new devicesnamely Carbon Nano Tube Field Effect transistors (CNTFETs) can be used for design of different digital circuits. In this paper, subthreshold leakage power of dual chiral CNTFET based domino circuit is investigated and also the results are compared with single chiral CNTFET domino circuits. For better performance, threshold voltage of CNTFET in critical path is varied by changing the diameter or chirality of carbon nanotube. Subthreshold leakage power saving in dual chiral standard and LECTOR based domino circuits for OR2, OR4, OR8 & OR16 for low temperature (25°C) & low input ranges from 90.36- 95.96% and from 91.97-97.3%; for low temperature & high input ranges from 90.66-95.23% and from 92.85-96.39%; for high temperature (110°C) & low input ranges from 89.24- 99.73% and from 27.5-99.83%; for high temperature & high input ranges from 89.65-97.86% and from 91.85-99.76% when compared with single chiral standard and LECTOR based domino circuits respectively.

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