Process‐induced variability modeling of subthreshold leakage power considering device stacking

2020 ◽  
Vol 48 (5) ◽  
pp. 739-749
Author(s):  
Anala M. Reddy ◽  
B.P. Harish
Keyword(s):  
Leakage Power ◽  
Variability Modeling ◽  
Device Stacking ◽  
Subthreshold Leakage

Full-Chip Subthreshold Leakage Power Prediction and Reduction Techniques for Sub-0.18-<tex>$mu$</tex>m CMOS

2004 ◽  
Vol 39 (3) ◽  
pp. 501-510 ◽  
Author(s):  
S. Narendra ◽  
V. De ◽  
S. Borkar ◽  
D.A. Antoniadis ◽  
A.P. Chandrakasan
Keyword(s):  
Leakage Power ◽  
Power Prediction ◽  
Reduction Techniques ◽  
Subthreshold Leakage

scholarly journals Design of CNTFET Based Domino Wide OR Gates Using Dual Chirality for Reducing Subthreshold Leakage Current

2021 ◽  
Author(s):  
Vijay Kumar Magraiya ◽  
Tarun Kumar Gupta ◽  
Bharat Garg
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
Leakage Current ◽  
Field Effect Transistors ◽  
Leakage Power ◽  
High Input ◽  
Low Input ◽  
Prime Concern ◽  
Subthreshold Leakage ◽  
Domino Circuits

Abstract The leakage current is prime concern in the modern portable battery operated device. However, various techniques are presented and performance is evaluated using MOSFET and FinFET devices. To further reduce leakage current for improved battery backup in portable devices, new devicesnamely Carbon Nano Tube Field Effect transistors (CNTFETs) can be used for design of different digital circuits. In this paper, subthreshold leakage power of dual chiral CNTFET based domino circuit is investigated and also the results are compared with single chiral CNTFET domino circuits. For better performance, threshold voltage of CNTFET in critical path is varied by changing the diameter or chirality of carbon nanotube. Subthreshold leakage power saving in dual chiral standard and LECTOR based domino circuits for OR2, OR4, OR8 & OR16 for low temperature (25°C) & low input ranges from 90.36- 95.96% and from 91.97-97.3%; for low temperature & high input ranges from 90.66-95.23% and from 92.85-96.39%; for high temperature (110°C) & low input ranges from 89.24- 99.73% and from 27.5-99.83%; for high temperature & high input ranges from 89.65-97.86% and from 91.85-99.76% when compared with single chiral standard and LECTOR based domino circuits respectively.

scholarly journals Performance Comparison of Digital Circuits Using Subthreshold Leakage Power Reduction Techniques

2017 ◽  
Vol 14 (1) ◽  
pp. 74 ◽  
Author(s):  
B. Kalagadda ◽  
N. Muthyala ◽  
K.K. Korlapati
Keyword(s):  
Power Dissipation ◽  
Digital Circuits ◽  
Digital Circuit ◽  
Performance Comparison ◽  
Power Reduction ◽  
Leakage Power ◽  
Nand Gate ◽  
Reduction Techniques ◽  
Half Adder ◽  
Subthreshold Leakage

Complementary metal-oxide semiconductors (CMOS), stack, sleep and sleepy keeper techniques are used to control sub-threshold leakage. These effective low-power digital circuit design approaches reduce the overall power dissipation. In this paper, the characteristics of inverter, twoinput negative-AND (NAND) gate, and half adder digital circuits were analyzed and compared in 45nm, 120nm, 180nm technology nodes by applying several leakage power reduction methodologies to conventional CMOS designs. The sleepy keeper technique when compared to other techniques dissipates less static power. The advantage of the sleepy keeper technique is mainly its ability to preserve the logic state of a digital circuit while reducing subthreshold leakage power dissipation. 

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