Drain current local variability analysis in nanoscale junctionless FinFETs utilizing a compact model

2020 ◽  
Vol 170 ◽  
pp. 107835
Author(s):  
T.A. Oproglidis ◽  
D.H. Tassis ◽  
A. Tsormpatzoglou ◽  
G. Ghibaudo ◽  
C.A. Dimitriadis
Keyword(s):  
Drain Current ◽  
Compact Model ◽  
Variability Analysis ◽  
Local Variability

scholarly journals A Unified Model of Drain Current Local Variability due to Channel Length Fluctuation for an n-Channel EδDC MOS Transistor

2021 ◽  
Author(s):  
Sarmista Sengupta ◽  
Soumya Pandit
Keyword(s):  
Threshold Voltage ◽  
Computer Aided Design ◽  
Drain Current ◽  
Channel Length ◽  
Model Verification ◽  
Silicon On Insulator ◽  
Compact Model ◽  
Random Fluctuation ◽  
Mos Transistor ◽  
Local Variability

Abstract A drain current local variability compact model due to random fluctuation of channel length induced by line edge roughness/line width roughness ( LER / LWR ) is derived here. The random fluctuation of channel length leads to correlated fluctuations of threshold voltage and effective mobility of the current carriers. Therefore, an unified compact model is required to combine all the causes. Our model is based on the principle of propagation of variance. For the model verification purpose, calibrated technology computer aided design ( TCAD ) simulation platform is extensively used for all possible bias regions and several LER profile parameters. Channel profile optimization is critically studied aiming reduction of ID variability. The model is further extended for SOI (Silicon-on-insulator) transistor and validated with literature data of threshold voltage and on-current variability.

scholarly journals Sensitivity Study of Polysilicon Nanowire Based on Scattering and Quantum Mechanics Models

2018 ◽  
Vol 201 ◽  
pp. 01002
Author(s):  
Aanand ◽  
Gene Sheu ◽  
Syed Sarwar Imam ◽  
Shao Wei Lu ◽  
Shao-Ming Yang ◽  
...  
Keyword(s):  
Quantum Mechanics ◽  
Gate Voltage ◽  
Drain Current ◽  
Sensitivity Study ◽  
Compact Model ◽  
Current Sensitivity ◽  
Back Gate ◽  
Mechanics Model ◽  
Theoretical Predictions ◽  
Current Characteristics

In this paper, we report nanowire drain saturation current sensitivity property to measure femtomol level change in drain current due to different proteins i.e. DNA with numerical simulation and fabricated polysilicon nanowire based on the theoretical predictions. In addition, the drain current will also be affected by the back-gate voltage and will increase as the back-gate voltage increases. A 3-dimensional Synopsis tool is used to investigate the drain current behavior for a polysilicon nanowire. The scattering compact model reported result of detailed numerical calculation shows in good agreement, indicating the usefulness of scattering compact model. Whereas 3D synopsis unable to explain the whole region of the drain current characteristics in linear region which uses quantum mechanics model approach.

Analytical Drain Current Compact Model in the Depletion Operation Region of Short-Channel Triple-Gate Junctionless Transistors

2017 ◽  
Vol 64 (1) ◽  
pp. 66-72 ◽  
Author(s):  
Theodoros A. Oproglidis ◽  
Andreas Tsormpatzoglou ◽  
Dimitrios H. Tassis ◽  
Theano A. Karatsori ◽  
Sylvain Barraud ◽  
...  
Keyword(s):  
Drain Current ◽  
Compact Model ◽  
Short Channel ◽  
Junctionless Transistors

scholarly journals Compact modeling of strained GAA SiNW

2019 ◽  
Vol 14 (1) ◽  
pp. 241
Author(s):  
Fatimah K. A Hamid ◽  
N. Ezaila Alias ◽  
R. Ismail ◽  
M. Anas Razali
Keyword(s):  
Threshold Voltage ◽  
Silicon Nanowire ◽  
Current Model ◽  
Drain Current ◽  
Cmos Technology ◽  
Compact Model ◽  
Compact Modeling ◽  
Smoothing Function ◽  
Inversion Charge ◽  
A Charge

<span>Strain-based on advanced MOSFET is a promising candidate for the future of CMOS technology. A numerical model is not favorable compared to a compact model because it cannot be integrated into most simulator software. Thus, a compact model is proposed to overcome the shortcomings in the analytical model. In this paper, a charge-based compact model is presented for long-channel strained Gate-All-Around Silicon Nanowire (GAA SiNW) from an undoped channel to a doped body. The model derivation is based on an inversion charge which has been solved explicitly using the smoothing function. The drain current model is formulated from Pao Sah’s dual integral which is formed in terms of inversion charge at the drain and source terminals. The proposed model has been extensively verified with the numerical simulator data. The strained effect on the electrical parameters are studied based on inversion charge, threshold voltage and current-voltage (I-V) characteristics. Results show that the current, the inversion charge and the threshold voltage can be greatly improved by the strain. The threshold voltage was reduced approximately 40% from the conventional GAA SiNW. Moreover, the inversion charge was improved by 30 % and the on-state current has doubled compared to unstrained device.</span>

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