Influence of Diverse Post-Trench Processes on the Electrical Performance of 4H-SiC MOS Structures

2014 ◽  
Vol 778-780 ◽  
pp. 595-598 ◽  
Author(s):  
Christian T. Banzhaf ◽  
Michael Grieb ◽  
Achim Trautmann ◽  
Anton J. Bauer ◽  
Lothar Frey
Keyword(s):  
Dielectric Breakdown ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Electrical Performance ◽  
Breakdown Field ◽  
Static Capacitance ◽  
Capacitance Voltage ◽  
Oxide Deposition ◽  
Mos Structures ◽  
Field Strengths

This paper focuses on the evaluation of subsequent process steps (post-trench processes, PTPs) after 4H silicon carbide (4H-SiC) trench etching with respect to the electrical performance of trenched gate metal oxide semiconductor field effect transistors (Trench-MOSFETs). Two different types of PTP were applied after 4H-SiC trench formation, a high temperature post-trench anneal (PTA) [1] and a sacrificial oxidation (SacOx) [2]. We found significantly improved electrical properties of Planar-MOS structures using a SacOx as PTP, prior to gate oxide deposition. Besides excellent quasi-static capacitance-voltage (QSCV) behavior even at T = 250 °C, charge-to-breakdown (QBD) results up to 8.8 C/cm2 at T = 200 °C are shown to be similar on trenched surfaces as well as on untrenched surfaces of SacOx-treated Planar-MOS structures. Moreover, dielectric breakdown field strengths up to 12 MV/cm have been measured on Planar-MOS structures. However, thick bottom oxide Trench-MOS structures indicate best dielectric breakdown field strengths of 9.5 MV/cm when using a trench shape rounding PTA as the PTP.

Characterization of Diverse Gate Oxides on 4H-SiC 3D Trench-MOS Structures

2013 ◽  
Vol 740-742 ◽  
pp. 691-694 ◽  
Author(s):  
Christian T. Banzhaf ◽  
Michael Grieb ◽  
Achim Trautmann ◽  
Anton J. Bauer ◽  
Lothar Frey
Keyword(s):  
Silicon Dioxide ◽  
Dielectric Breakdown ◽  
Interface State ◽  
Oxide Semiconductor ◽  
Breakdown Field ◽  
Flat Band ◽  
Mos Devices ◽  
State Densities ◽  
Mos Structures

This study focuses on the characterization of silicon dioxide (SiO2) layers, either thermally grown or deposited on trenched 100 mm 4H-silicon carbide (SiC) wafers. We evaluate the electrical properties of silicon dioxide as a gate oxide (GOX) for 3D metal oxide semiconductor (MOS) devices, such as Trench-MOSFETs. Interface state densities (DIT) of 1*1011cm-2eV-1under flat band conditions were determined using the hi-lo CV-method [1]. Furthermore, current-electric field strength (IE) measurements have been performed and are discussed. Trench-MOS structures exhibited dielectric breakdown field strengths up to 10 MV/cm.

Hole Trapping in the NBTI Characteristic of SiC MOSFETs

2018 ◽  
Vol 924 ◽  
pp. 667-670
Author(s):  
Yan Jing He ◽  
Hong Liang Lv ◽  
Xiao Yan Tang ◽  
Qing Wen Song ◽  
Yi Meng Zhang ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Threshold Voltage Shift ◽  
Hole Trapping ◽  
Primary Mechanism ◽  
Capacitance Voltage ◽  
Cv Measurements ◽  
P Type

P-type implanted metal oxide semiconductor capacitors (MOSCAPs) and metal oxide semiconductor field effect transistors (MOSFETs) have been fabricated. The characteristics of hole trapping at the interface of SiO2/SiC are investigated through capacitance-voltage (CV) measurements with different starting voltages. The negative shift voltage ∆Vshift and the hysteresis voltages ∆VH which caused by the hole traps in the MOSCAPs and MOSFETs are extracted from CV results. The results show that the hole traps extracted from MOSCAPs are larger than the that extracted from the threshold voltage shift in the MOSFETs. It suggests holes trapping are the primary mechanism contributing to the NBTI, but not all the holes work. Part of the hole traps are compensation by sufficient electrons in the MOSFET structure.

1.4kV Double-Implanted MOSFETs Fabricated on 4H-SiC(000-1)

2011 ◽  
Vol 679-680 ◽  
pp. 607-612 ◽  
Author(s):  
Hiroshi Kono ◽  
Takuma Suzuki ◽  
Kazuto Takao ◽  
Masaru Furukawa ◽  
Makoto Mizukami ◽  
...  
Keyword(s):  
Room Temperature ◽  
Dielectric Breakdown ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Drain Voltage ◽  
Mos Capacitor ◽  
Time Dependent Dielectric Breakdown ◽  
Blocking Voltage ◽  
Switching Characteristics

1.2 mm × 1.2 mm and 2.7 mm × 2.7 mm silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. 1.2 mm × 1.2 mm DIMOSFETs were characterized from room temperature to 150°C. At room temperature, the specific on-resistance of this MOSFET was 5.7 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The blocking voltage of this MOSFET was 1450 V based on the avalanche current. At 150 °C, the specific on-resistance increased from 5.7 mΩcm2 to 9.1 mΩcm2 and the threshold voltage decreased from 4.9 V to 4.1 V. The blocking voltage increased from 1450V to 1500V. 2.7 mm × 2.7 mm DIMOSFETs were also characterized at room temperature. They showed a specific on-resistance of 8.0 mΩcm2 at a gate bias of 20 V and a drain voltage of 1 V. The blocking voltage of this device was 1550 V, which was determined by the avalanche current. The time-zero dielectric breakdown (TZDB) and time-dependent dielectric breakdown (TDDB) characteristics of 180 μm × 180 μm MOS capacitor were estimated. At room temperature (RT), TZDB was 9.3 MV/cm and the charge to breakdown value of 63% cumulative failure (Qbd) was 72 C/cm2. The temperature dependence of Qbd measurements showed that it deceased from 72 C/cm2 at RT to 14 C/cm2 at 250 °C. Switching characteristics of 1.2 mm × 1.2 mm DIMOSFETs were obtained by the double-pulse measurements. The turn-on time and the turn-off time were 36 nsec and 53 nsec, respectively.

Electrical Properties of Metal-Oxide-Semiconductor (MOS) Structures on 4H-SiC(0001) Formed by Oxidizing Pre-Deposited SixNy

2007 ◽  
Vol 556-557 ◽  
pp. 647-650 ◽  
Author(s):  
Jeong Hyun Moon ◽  
Dong Hwan Kim ◽  
Ho Keun Song ◽  
Jeong Hyuk Yim ◽  
Wook Bahng ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Metal Oxide ◽  
Current Density ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Electrical Field ◽  
Mos Capacitors ◽  
Dielectric Layers ◽  
Capacitance Voltage ◽  
Mos Structures

We have fabricated advanced metal-oxide-semiconductor (MOS) capacitors with ultra thin (5 nm) remote-PECVD SixNy dielectric layers and investigated electrical properties of nitrided SiO2/4H-SiC interface after oxidizing the SixNy in dry oxygen at 1150 °C for 30, 60, 90 min. Improvements of electrical properties have been revealed in capacitance-voltage (C-V) and current density-electrical field (J-E) measurements in comparison with dry oxide. The improvements of SiC MOS capacitors formed by oxidizing the pre-deposited SixNy have been explained in this paper.

TDDB Lifetime Enhancement in SiC-MOSFETs under Gate-Switching Pperation

2020 ◽  
Vol 1004 ◽  
pp. 665-670
Author(s):  
Eiichi Murakami ◽  
Tatsuya Takeshita ◽  
Kazuhiro Oda
Keyword(s):  
Dielectric Breakdown ◽  
Defect Density ◽  
Field Effect Transistors ◽  
Stress Test ◽  
Anomalous Behavior ◽  
Oxide Semiconductor ◽  
Continuous Increase ◽  
Hole Trapping ◽  
The Impact ◽  
Lifetime Enhancement

Gate oxide integrity (GOI) are the most important concern in automotive applications of SiC-metal-oxide-semiconductor field-effect transistors (MOSFETs). As well as for the so-called B-mode defect density reduction, the time-dependent dielectric breakdown (TDDB) mechanism including the B-mode should be clarified in comparison to Si-MOSFETs. We have reported an anomalous behavior in the form of a continuous increase in the gate current during a Fowler-Nordheim stress test of commercially available SiC-MOSFETs, which we attributed to hole trapping near the SiO2/SiC interface. In this paper, the impact of this phenomenon on the TDDB lifetime is investigated, and the effects of AC on the TDDB lifetime enhancement in SiC-MOSFET under gate-switching operations (1 kHz and 100 kHz, at room temperature) are reported.

Shallow Traps at P-Doped SiO2/4H-SiC(0001) Interface

2011 ◽  
Vol 679-680 ◽  
pp. 338-341 ◽  
Author(s):  
Dai Okamoto ◽  
Hiroshi Yano ◽  
Shinya Kotake ◽  
Tomoaki Hatayama ◽  
Takashi Fuyuki
Keyword(s):  
Photoelectron Spectroscopy ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Interface Traps ◽  
Channel Mobility ◽  
X Ray ◽  
Capacitance Voltage ◽  
Shallow Traps

We report on electrical and physical investigations aimed to clarify the mechanisms behind the high channel mobility of 4H-SiC metal–oxide–semiconductor field-effect transistors processed with POCl3 annealing. By low-temperature capacitance–voltage analysis, we found that the shallow interface traps are effectively removed by P incorporation. Using x-ray photoelectron spectroscopy, we found that the three-fold coordinated P atoms exist at the oxide/4H-SiC interface. The overall results suggest that P atoms directly remove the Si–Si bonds and thus eliminate the near-interface traps.

Impact of Post-Trench Processing on the Electrical Characteristics of 4H-SiC Trench-MOS Structures with Thick Top and Bottom Oxides

2015 ◽  
Vol 821-823 ◽  
pp. 753-756 ◽  
Author(s):  
Christian T. Banzhaf ◽  
Michael Grieb ◽  
Martin Rambach ◽  
Anton J. Bauer ◽  
Lothar Frey
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Inert Gas ◽  
Breakdown Field ◽  
Wafer Surface ◽  
Mos Devices ◽  
Uniform Current ◽  
Thin Gate Oxide ◽  
Mos Structures

This study focuses on the evaluation of different post-trench processes (PTPs) for Trench-MOSFETs. Thereto, two different types of inert gas anneals at process temperatures above 1250 °C are compared to a sacrificial oxidation as PTP. The fabricated 4H-SiC Trench-MOS structures feature a thick silicon dioxide (SiO2) both at the wafer surface (‘top’) and in the bottom of the trenches (‘bottom’) in order to characterize only the thin gate oxide at the trenched sidewalls. It is shown that an inert gas anneal at a process temperature between 1400 °C and 1550 °C yields uniform current/electric field strength (IE) values and excellent dielectric breakdown field strengths up to 12 MV/cm using a SiO2 gate oxide of approximately 40 nm thickness. Charge-to-breakdown (QBD) measurements at a temperature T of 200 °C confirm the necessity of a high temperature inert gas anneal after 4H-SiC trench etching in order to fabricate reliable Trench-MOS devices. QBD values up to 16.2 C/cm² have been measured at trenched and high temperature annealed sidewalls, which is about twice the measured maximum QBD value of the corresponding planar reference MOS structure. The capacitive MOS interface characterization points out the need for a sacrificial oxidation subsequent to a high temperature inert gas anneal in order to ensure a high quality MOS interface with excellent electrical properties.

Charge Trapping and Degradation of High Permittivity TiO2 Dielectric Metal-Oxide-Semiconductor Field Effect Transistors

1996 ◽  
Vol 448 ◽  
Author(s):  
Hyeon-Saeg Kim ◽  
S.A. Campbell ◽  
D.C. Gilmer ◽  
D.L. Polla
Keyword(s):  
Dielectric Breakdown ◽  
Field Effect Transistors ◽  
Tunneling Current ◽  
Chemical Vapor ◽  
Charge Trapping ◽  
Interface States ◽  
Gate Insulator ◽  
Oxide Semiconductor ◽  
Constant Current ◽  
Organic Chemical

AbstractSuitable replacement materials for ultrathin SiO2 in deeply scaled MOSFETs such as lattice polarizable films, which have much higher permittivities than SiO2, have bandgaps of only 3.0 to 4.0 eV. Due to these small bandgaps, the reliability of these films as a gate insulator is a serious concern. Ramped voltage, time dependent dielectric breakdown, and capacitance-voltage measurements were done on 190Å layers of TiO2 which were deposited through the metal-organic chemical vapor deposition of titanium tetrakis-isopropoxide. Measurements of the high and low frequency capacitance indicate that virtually no interface states are created during constant current injection stress. The increase in leakage upon electrical stress suggests that uncharged, near-interface states may be created in the TiO2 film near the SiO2 interfacial layer that allow a tunneling current component at low bias.

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