Secondary impact ionization and device aging in deep submicron MOS devices with various transistor architectures

Computer simulations were done extensively in order to study nonlinear dynamics of laser and non-equilibrium electron-hole plasma interaction in deep submicron n-MOSFET silicon devices. We constructed the modified Duffing kind of nonlinear electron-hole plasma oscillator equation. Nonlinear characteristics of electron-hole plasma by impact ionization in submicron devices manifest a wide diversity of complex chaotic behavior. Collision frequency is found to be the dominant parameter to influence the bifurcation, chaos, hysteresis and bistable effects of electron-hole plasma at deep submicron devices. Small windows of higher period cascade above the critical value of laser parameter (α1α2) in the chaos region are observed. Non-equilibrium electron-hole plasma shows much chaotic regime at lower value of laser frequency (δ). Hysteresis and bistable region of electron-hole plasma are also presented and the conditions for their occurrence are identified. The unstable region completely merge at higher value of effective collision frequency (γ).

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VLSI Dynamic nMOS design constraints due to drain induced primary and secondary impact ionization

10.1109/iedm.1979.189527 ◽

1979 ◽

Cited By ~ 2

Author(s):

P.K. Chatterjee

Keyword(s):

Impact Ionization ◽

Design Constraints ◽

Secondary Impact

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Applications of impact-ionization metal–oxide-semiconductor (I-MOS) devices to circuit design

Current Applied Physics ◽

10.1016/j.cap.2009.07.001 ◽

2010 ◽

Vol 10 (2) ◽

pp. 444-451 ◽

Cited By ~ 7

Author(s):

Woo Young Choi

Keyword(s):

Metal Oxide ◽

Circuit Design ◽

Impact Ionization ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Mos Devices

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A NEW APPROACH TO CHARACTERIZE AND PREDICT LIFETIME OF DEEP-SUBMICRON NMOS DEVICES

International Journal of High Speed Electronics and Systems ◽

10.1142/s0129156406003667 ◽

2006 ◽

Vol 16 (01) ◽

pp. 315-323

Author(s):

ZHI CUI ◽

JUIN J. LIOU ◽

YUN YUE ◽

HEI WONG

Keyword(s):

Power Law ◽

Tunneling Current ◽

Deep Submicron ◽

Lifetime Estimation ◽

New Approach ◽

Base Current ◽

Mos Devices ◽

Current Stressing ◽

Substrate Current

Experimental results are presented to indicate that the widely used power-law models for lifetime estimation are questionable for deep submicron (< 0.25 μm) MOS devices, particularly for the case of large substrate current stressing. This observation is attributed to the presence of current components, such as the gate tunneling current and base current of parasitic bipolar transistor, that do not induce device degradation. A more effective extrapolation method is proposed as an alternative for the reliability characterization of deep-submicron MOS devices.

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Design of Low Power Less Leakage Quarternary Adder Using CMOS

International Journal of Advanced Research in Science, Communication and Technology ◽

10.48175/ijarsct-2316 ◽

2021 ◽

pp. 110-121

Author(s):

M. Sutha ◽

Dr. R. Nirmala ◽

Dr. E. Kamalavathi

Keyword(s):

Low Power ◽

Impact Ionization ◽

Vlsi Design ◽

Cmos Technology ◽

Surface Scattering ◽

Short Channel Effects ◽

Short Channel ◽

Mos Devices ◽

Channel Effects ◽

Quaternary Adder

In VLSI, design and implementation of circuits with MOS devices and binary logic are quite usual. The Main Objective is to design a low power and minimum leakage Quaternary adder. The VLSI field consists of Multi-valued logic (MVL) such as ternary and Quaternary Logic (QTL). The Failures such as Short Channel Effects (SCE) Impact-ionization and surface scattering are in normalized aspects. The Quaternary radix on MVL (multi-valued logic) monitors and reduces the area. The Quaternary (four-valued) logic converts the quaternary signals and binary signals produced by the by the existing binary circuits. The Proposed is carried out with LTSPICE tool and CMOS technology.

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