Study the etching mechanism of photosensitive dry film on depositing gold during fabrication of printed circuit board

1997 ◽  
Vol 51 (1) ◽  
pp. 70-74 ◽  
Author(s):  
G.S. Tzeng ◽  
S.C. Jang ◽  
Y.Y. Wang ◽  
C.C. Wan
Keyword(s):  
Printed Circuit Board ◽  
Circuit Board ◽  
Printed Circuit ◽  
Etching Mechanism ◽  
Dry Film

Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration

2018 ◽  
Vol 15 (4) ◽  
pp. 141-147 ◽  
Author(s):  
Cheng-Ta Ko ◽  
Henry Yang ◽  
John Lau ◽  
Ming Li ◽  
Margie Li ◽  
...  
Keyword(s):  
Seed Layer ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Heterogeneous Integration ◽  
Assembly Process ◽  
Molding Compound ◽  
Printed Circuit ◽  
Chip Size ◽  
Design Materials ◽  
Dry Film

Abstract The design, materials, process, and fabrication of a heterogeneous integration of four chips by a fan-out panel-level packaging (FOPLP) method are investigated in this study. Emphasis is placed on (1) the application of a dry-film epoxy molding compound for molding the chips and (2) the application of a special assembly process called uni-substrate-integrated package for fabricating the redistribution layers (RDLs) of the FOPLP. The Ajinomoto build-up film is used as the dielectric of the RDLs and is built up by the semiadditive process. Electroless Cu is used to make the seed layer, laser direct imaging is used for opening the photoresist, and printed circuit board (PCB) Cu plating is used for making the conductor wiring of the RDLs. The panel dimensions are 508 × 508 mm. The package dimensions of the FOPLP are 10 × 10 mm. The large chip size and the small chip sizes are, respectively, 5 × 5 mm and 3 × 3 mm. The uniqueness of this study is that all the processes are carried out by using the PCB equipment.

The applicability of electrodeposited photoresists in producing ultra‐fine lines using sputtered seeding layers

Circuit World ◽  
2002 ◽  
Vol 28 (2) ◽  
pp. 11-13 ◽  
Author(s):  
Paavo Jalonen ◽  
Aulis Tuominen
Keyword(s):  
Printed Circuit Board ◽  
Circuit Board ◽  
Core Material ◽  
Quality Properties ◽  
Printed Circuit ◽  
Printed Circuit Board Manufacturing ◽  
Coating Method ◽  
Film Method ◽  
Seed Layers ◽  
Dry Film

Photolithographic techniques are universally employed in multi‐layer printed circuit board manufacturing. The growing demand for miniaturization of electronics means that finer lines and smaller vias are increasingly required and these very fine lines on the substrate are increasingly difficult to produce by conventional means. One very promising means of meeting these fine line requirements is via the etching of sputtered thin films on a substrate and then growing copper on these lines using an additive method. In this work we tested the capability of an electrodeposited, positive‐acting photoresist for patterning thin film circuits on sputtered seed layers such as chromium. A fully additive electroless copper was then used to produce the copper lines. Epoxy reinforced fibreglass was used as a core material. The performance and quality properties of the process were examined, along with limitations of the process when compared with both a conventional dry film method and a spin coating method.

Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration

2018 ◽  
Vol 2018 (1) ◽  
pp. 000057-000063 ◽  
Author(s):  
Cheng-Ta Ko ◽  
Henry Yang ◽  
John Lau ◽  
Ming Li ◽  
Margie Li ◽  
...  
Keyword(s):  
Seed Layer ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Heterogeneous Integration ◽  
Additive Process ◽  
Molding Compound ◽  
Printed Circuit ◽  
Chip Size ◽  
Design Materials ◽  
Dry Film

Abstract The design, materials, process, and fabrication of a heterogeneous integration of 4 chips by a FOPLP (fanout panel-level packaging) method are investigated in this study. Emphasis is placed on (a) the application of a dry-film EMC (epoxy molding compound) for molding the chips, and (b) the application of a special assembly process called Uni-SIP (uni-substrate-integrated-package) for fabricating the RDLs (redistribution layers) of the FOPLP. The ABF (Ajinomoto build-up film) is used as the dielectric of the RDLs and is built up by the SAP (semi-additive process). The electroless Cu is used to make the seed layer, the LDI (laser direct imaging) is used for opening the photoresist, and the PCB (printed circuit board) Cu plating is used for making the conductor wiring of the RDLs. The panel dimensions are 508mm × 508mm. The package dimensions of the FOPLP are 10mm × 10mm. The large chip size and the small chip sizes are, respectively 5mm × 5mm and 3mm × 3mm.

Hardness of Rinse Water and Swelling Behavior of Dry Film Photo-Resist

2011 ◽  
Author(s):  
Song-I Kim ◽  
JinWoo Heo ◽  
YunHee Kim ◽  
Yeonseop Yu ◽  
ChungSik Choi ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Focused Ion Beam ◽  
Printed Circuit Board ◽  
Divalent Cations ◽  
Ion Beam ◽  
Hard Water ◽  
Swelling Behavior ◽  
Circuit Board ◽  
Printed Circuit ◽  
Dry Film

Abstract We investigated the swelling behavior of dry film photoresist in rinse process after development by varying the hardness of water. We inspected the appearance of sidewalls and the foot of the resist. We also measured the depth of once swollen resist using a FIB (focused ion beam) and analyzed the chemistry of the resist after rinse using an XPS (X-ray photoelectron spectroscopy). We experimentally proved that divalent cations such as Ca2+ and Mg2+ in hard water could be exchanged with Na+ on the resist surface and quench swelling of the exposed resist in rinse. This study indicates that the use of hard water in rinse process may result in better line definition and resolution in PCB (printed circuit board).

scholarly journals Dry Film Photoresist Application to a Printed Circuit Board (Pcb) using a Maskless Photolithography Method

2019 ◽  
Vol 10 (5) ◽  
pp. 1033
Author(s):  
Dedi Suwandi ◽  
Rofan Aziz ◽  
Agus Sifa ◽  
Emin Haris ◽  
Jos Istiyanto ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Circuit Board ◽  
Printed Circuit ◽  
Dry Film ◽  
Dry Film Photoresist

Characteristics of Radiated Emission from a Printed Circuit Board with a Slit

2012 ◽  
Vol 132 (6) ◽  
pp. 404-410 ◽  
Author(s):  
Kenichi Nakayama ◽  
Kenichi Kagoshima ◽  
Shigeki Takeda
Keyword(s):  
Printed Circuit Board ◽  
Circuit Board ◽  
Printed Circuit ◽  
Radiated Emission

Confirming the Signal Integrity in Transmission of Digital Signals on Microstrip Straight Circuits via the Eye Diagrams

2014 ◽  
Vol 5 (1) ◽  
pp. 737-741
Author(s):  
Alejandro Dueñas Jiménez ◽  
Francisco Jiménez Hernández
Keyword(s):  
Integrated Circuits ◽  
Printed Circuit Board ◽  
Signal Integrity ◽  
High Volume ◽  
Information Storage ◽  
Circuit Board ◽  
Electromagnetic Simulation ◽  
Electronic Systems ◽  
Digital Signals ◽  
Printed Circuit

Because of the high volume of processing, transmission, and information storage, electronic systems presently requires faster clock speeds tosynchronizethe integrated circuits. Presently the “speeds” on the connections of a printed circuit board (PCB) are in the order of the GHz. At these frequencies the behavior of the interconnects are more like that of a transmission line, and hence distortion, delay, and phase shift- effects caused by phenomena like cross talk, ringing and over shot are present and may be undesirable for the performance of a circuit or system.Some of these phrases were extracted from the chapter eight of book “2-D Electromagnetic Simulation of Passive Microstrip Circuits” from the corresponding author of this paper.

Root Cause Analysis of a Connector Time-Delayed Fracture

2015 ◽  
Author(s):  
Prabjit Singh ◽  
Ying Yu ◽  
Robert E. Davis
Keyword(s):  
Printed Circuit Board ◽  
Ceramic Substrate ◽  
Circuit Board ◽  
Delayed Fracture ◽  
Ceramic Substrates ◽  
Printed Circuit ◽  
Root Cause ◽  
Chip Carrier ◽  
Electrical Connections ◽  
Grain Boundary Grooves

Abstract A land-grid array connector, electrically connecting an array of plated contact pads on a ceramic substrate chip carrier to plated contact pads on a printed circuit board (PCB), failed in a year after assembly due to time-delayed fracture of multiple C-shaped spring connectors. The land-grid-array connectors analyzed had arrays of connectors consisting of gold on nickel plated Be-Cu C-shaped springs in compression that made electrical connections between the pads on the ceramic substrates and the PCBs. Metallography, fractography and surface analyses revealed the root cause of the C-spring connector fracture to be plating solutions trapped in deep grain boundary grooves etched into the C-spring connectors during the pre-plating cleaning operation. The stress necessary for the stress corrosion cracking mechanism was provided by the C-spring connectors, in the land-grid array, being compressed between the ceramic substrate and the printed circuit board.

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