scholarly journals A 2.5-GHz 1-V High Efficiency CMOS Power Amplifier IC with a Dual-Switching Transistor and Third Harmonic Tuning Technique

Electronics ◽  
2019 ◽  
Vol 8 (1) ◽  
pp. 69 ◽  
Author(s):  
Taufiq Alif Kurniawan ◽  
Toshihiko Yoshimasu
Keyword(s):  
Power Amplifier ◽  
High Efficiency ◽  
Low Voltage ◽  
Supply Voltage ◽  
Drain Current ◽  
Cmos Technology ◽  
Back Gate ◽  
Third Harmonic ◽  
Power Added Efficiency ◽  
Switching Transistor

This paper presents a 2.5-GHz low-voltage, high-efficiency CMOS power amplifier (PA) IC in 0.18-µm CMOS technology. The combination of a dual-switching transistor (DST) and a third harmonic tuning technique is proposed. The DST effectively improves the gain at the saturation power region when the additional gain extension of the secondary switching transistor compensates for the gain compression of the primary one. To achieve high-efficiency performance, the third harmonic tuning circuit is connected in parallel to the output load. Therefore, the flattened drain current and voltage waveforms are generated, which in turn reduce the overlapping and the dc power consumption significantly. In addition, a 0.5-V back-gate voltage is applied to the primary switching transistor to realize the low-voltage operation. At 1 V of supply voltage, the proposed PA has achieved a power added efficiency (PAE) of 34.5% and a saturated output power of 10.1 dBm.

scholarly journals Analysis and Compensation of the AM-AM and AM-PM Distortion for CMOS Cascode Class-E Power Amplifier

2009 ◽  
Vol 2009 ◽  
pp. 1-9 ◽  
Author(s):  
Wen An Tsou ◽  
Wen Shen Wuen ◽  
Tzu Yi Yang ◽  
Kuei Ann Wen
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Signal Source ◽  
Nonlinear Capacitance ◽  
Power Added Efficiency ◽  
Equivalent Impedance ◽  
Common Gate ◽  
Class E

Analysis and compensation methodology of the AM-AM and AM-PM distortion of cascode class-E power amplifiers are presented. A physical-based model is proposed to illustrate that the nonlinear capacitance and transconductance cause the AM-AM and AM-PM distortion when modulating the supply voltage of the PA. A novel methodology that can reduce the distortion is also proposed. By degenerating common-gate transistor into a resistor, the constant equivalent impedance is obtained so that the AM-AM and AM-PM distortion is compensated. An experimental prototype of 2.6 GHz cascode class-E power amplifier with the AM-AM and AM-PM compensation has been integrated in a 0.18 μm CMOS technology, occupies a total die area of 1.6 mm2. It achieves a drain efficiency of 17.8% and a power-added efficiency of 16.6% while delivering 12 dBm of linear output power and drawing 31 mA from a 1.8 V supply. Finally, a co-simulation result demonstrated that, when the distortion of the PA has been compensated, the EVM is improved from −17 dB to −19 dB with an IEEE802.11a-like signal source.

scholarly journals Design of Class F Power Amplifier for 2.4ghz using Third Harmonics

2019 ◽  
Vol 8 (3) ◽  
pp. 7370-7375
Keyword(s):  
Power Amplifier ◽  
Large Scale ◽  
High Efficiency ◽  
Supply Voltage ◽  
Travelling Wave ◽  
Input Power ◽  
Engineering Research ◽  
Power Added Efficiency ◽  
Amplification Process ◽  
Class F

Historically, travelling wave tube amplifier (TWTA) has been a common type of Microwave amplifier used commonly in terrestrial and space application due to their high efficiency and power handling capacity. However due to their bulky nature and also being very expensive, it is difficult to use them commercially in a large scale. Inspired by the advantage such as very less development cost, minimum supply voltage, gradual degradation and numerous commercial applications, Solid State Power Amplifier (SSPA) has been the replacement to vacuum tube Technology. The efficiency of the amplifier is one of the most important task in the microwave engineering research. An important figure of merit, power-added efficiency (PAE), is the main focus. Hence in this paper, class F Power amplifier is designed for 2.4GHz frequency. Class F Amplifier is also called as wave shaping amplifier since the harmonics generated helps the amplification process. The class f PA is biased nearer to the class B amplifier (close cut-off area) so the transistor can move back and forth rapidly to produce the harmonics. The efficiency of class F amplifier depends on how many harmonics are used for the amplification process. Here, the amplification process is performed up to the third harmonics which provides 41.606 dBm output power with 27dBm input power. Also a gain of more than 20.277dBm is achieved when the input given is 27dBm. Several other results like reflection Coefficient and transmission coefficient simulations has also been provided with the power added efficiency (PAE) of 75.402 achieved has also been simulated.

A High Efficiency CMOS Power Amplfieir with a Diode Linearizer and Voltage Combining Transformers

2011 ◽  
Vol 110-116 ◽  
pp. 5500-5504
Author(s):  
Ki Jin Kim ◽  
Tae Ho Lim ◽  
S.H. Park ◽  
K. H. Ahn
Keyword(s):  
Power Amplifier ◽  
Insertion Loss ◽  
High Efficiency ◽  
Cmos Technology ◽  
High Current ◽  
Class Ab ◽  
Power Added Efficiency ◽  
Supply Condition ◽  
Saturation Power ◽  
Low Insertion Loss

This paper proposes a high efficiency power amplifier with a diode linearizer and voltage combining transformers in a standard 0.13-μm TSMC CMOS technology. The 3-D simulated transformer adopts multi-finger architecture which provides low insertion loss and allows high current capacity on the transformer. With the 4 differentially cascaded connected multi-finger transformers, the amplifier delivers more than 1W output power under 1.8 V supply condition. To enhance linearity of the power amplifier, the diode configuration bias circuit is used in this paper. With all integration of transformers, balun, diode bias circuits and same 4 diff-amps, the prototype Class AB Power Amplifier shows 32dBm saturation power at 2.4 GHz. Due to the diode linearizer the output P1dB is 30.8 dBm with 28 % Power Added Efficiency.

scholarly journals K-Band Hetero-Stacked Differential Cascode Power Amplifier with High Psat and Efficiency in 65 nm LP CMOS Technology

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 890
Author(s):  
Kyu-Jin Choi ◽  
Jae-Hyun Park ◽  
Seong-Kyun Kim ◽  
Byung-Sung Kim
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Common Source ◽  
Output Resistance ◽  
Power Added Efficiency ◽  
High Output ◽  
K Band

A K-band complementary metal-oxide-semiconductor (CMOS) differential cascode power amplifier is designed with the thin-oxide field effect transistor (FET) common source (CS) stage and thick-oxide FET common gate (CG) stage. Use of the thick-oxide CG stage affords the high supply voltage to 3.7 V and enables the high output power. Additionally, simple analysis shows that the gain degradation due to the low cut-off frequency of the thick-oxide CG FET can be compensated by the high output resistance of the thick-oxide FET if the inter-stage node is neutralized. The measured results of the proposed power amplifier demonstrate the saturated output power of the 23.3 dBm with the 31.3% peak power added efficiency (PAE) at 24 GHz frequency. The chip is fabricated in 65-nm low power (LP) CMOS technology and the chip size including all pads is 700 μm × 630 μm.

scholarly journals Research and Construct of Low Power, Excessive-Velocity Comparators using Cmos Generation with Low Deliver Voltages for Adcs

2019 ◽  
Vol 8 (6S) ◽  
pp. 286-291
Keyword(s):  
Low Power ◽  
High Efficiency ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Power Supply Voltage ◽  
Voltage Comparator ◽  
Analog To Digital ◽  
Ac Power ◽  
The Given

The evaluation of many comparator outcomes for the given requirement having excessive velocity using analog to digital converters is growing, this are controlled using CMOS comparators which are successful when delivering the low voltage with high efficiency. The comparators are primary part of numerous simple to computerized converters. The prerequisite for low-control, rapid simple to advanced converters is increasing. Thus comparators are generally utilized in the present innovation because of its quick operational speed and high precision. The quickly developing versatile gadget requires low power and high operational capacities which should be improved. A concise investigation of traditional double tail voltage comparator is done and dependent on that, a low power and region productive comparator is displayed. Another comparator is planned so as to decrease the postponement of ordinary comparators and diminish the power utilization of the gadget. Furthermore, the Reproduction is finished by Leather Treated Simple Plan Condition. At last we study about conventional dual tail voltage comparator which is done based on low power and area efficient comparator. In this simulation of proposed comparator is occurs a 180nm CMOS technology its consumes the power of 69µW at 1.2v Ac power supply voltage.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

Design of high-efficiency Hybrid Power Amplifier with concurrent F&F−1 class operations for 5G application

Frequenz ◽  
2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Meisam Tahmasbi ◽  
Farhad Razaghian ◽  
Sobhan Roshani
Keyword(s):  
Power Amplifier ◽  
High Efficiency ◽  
New Method ◽  
Power Added Efficiency ◽  
Hybrid Power ◽  
Novel Structure ◽  
Mode A

Abstract This paper presents a novel structure of Hybrid Power Amplifier (HPA) to operate in two arbitrary classes of operation at two desirable frequencies. The proposed HPA is designed in concurrent F&F−1 classes, simultaneously for 5G application. Presented HPA can solve the harmonics interference problem for concurrent F and F−1 classes and also for any arbitrary class of operation in desired frequencies. The designed HPA operates at 1.5 GHz frequency in the F class mode, while operates at 2.1 GHz frequency in the F−1 class mode. A new method is presented by using two diplexers to provide two paths for signal in different frequencies. Two parallel paths are used at the output of the HPA circuit, so the proposed HPA can operate at two classes. Two diplexers are used in the HPA to make proper isolation between the designed paths. In design of the proposed HPA, according to the utilized diplexers, the amplifier can operate between two arbitrary classes of operation at desired frequencies without any specific switch. The measured drain efficiency (DE) and power added efficiency (PAE) parameters are 57 and 51%, respectively at 2.1 GHz, while measured DE and PAE are 64 and 54%, respectively at 1.5 GHz.

scholarly journals A –5 dBm 400MHz OOK Transmitter for Wireless Medical Application

2014 ◽  
Vol 60 (2) ◽  
pp. 193-198
Author(s):  
M. Yousefi ◽  
D. Koozehkanani ◽  
H. Jangi ◽  
N. Nasirzadeh ◽  
J. Sobhi
Keyword(s):  
Energy Consumption ◽  
Power Amplifier ◽  
High Efficiency ◽  
Medical Application ◽  
Cmos Technology ◽  
High Energy ◽  
Data Rate ◽  
High Data Rate ◽  
Low Power Consumption ◽  
High Data

Abstract A 400 MHz high efficiency transmitter for wireless medical application is presented in this paper. Transmitter architecture with high-energy efficiencies is proposed to achieve high data rate with low power consumption. In the on-off keying transmitters, the oscillator and power amplifier are turned off when the transmitter sends 0 data. The proposed class-e power amplifier has high efficiency for low level output power. The proposed on-off keying transmitter consumes 1.52 mw at -5 dBm output by 40 Mbps data rate and energy consumption 38 pJ/bit. The proposed transmitter has been designed in 0.18μm CMOS technology.

scholarly journals Ladder-Based Synthesis and Design of Low-Frequency Buffer-Based CMOS Filters

Electronics ◽  
2021 ◽  
Vol 10 (23) ◽  
pp. 2931
Author(s):  
Waldemar Jendernalik ◽  
Jacek Jakusz ◽  
Grzegorz Blakiewicz
Keyword(s):  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Low Frequency ◽  
Cmos Technology ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Biomedical Sensors ◽  
Filter Synthesis ◽  
Cascade Method

Buffer-based CMOS filters are maximally simplified circuits containing as few transistors as possible. Their applications, among others, include nano to micro watt biomedical sensors that process physiological signals of frequencies from 0.01 Hz to about 3 kHz. The order of a buffer-based filter is not greater than two. Hence, to obtain higher-order filters, a cascade of second-order filters is constructed. In this paper, a more general method for buffer-based filter synthesis is developed and presented. The method uses RLC ladder prototypes to obtain filters of arbitrary orders. In addition, a set of novel circuit solutions with ultra-low voltage and power are proposed. The introduced circuits were synthesized and simulated using 180-nm CMOS technology of X-FAB. One of the designed circuits is a fourth-order, low-pass filter that features: 100-Hz passband, 0.4-V supply voltage, power consumption of less than 5 nW, and dynamic range above 60 dB. Moreover, the total capacitance of the proposed filter (31 pF) is 25% lower compared to the structure synthesized using a conventional cascade method (40 pF).

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