Tunnel field-effect transistors as energy-efficient electronic switches

Nature ◽  
2011 ◽  
Vol 479 (7373) ◽  
pp. 329-337 ◽  
Author(s):  
Adrian M. Ionescu ◽  
Heike Riel
Keyword(s):  
Energy Efficient ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Electronic Switches

Dirac-source field-effect transistors as energy-efficient, high-performance electronic switches

Science ◽  
2018 ◽  
Vol 361 (6400) ◽  
pp. 387-392 ◽  
Author(s):  
Chenguang Qiu ◽  
Fei Liu ◽  
Lin Xu ◽  
Bing Deng ◽  
Mengmeng Xiao ◽  
...  
Keyword(s):  
Energy Efficient ◽  
Field Effect ◽  
Electron Density Distribution ◽  
High Performance ◽  
Room Temperature ◽  
Supply Voltage ◽  
Field Effect Transistors ◽  
State Of The Art ◽  
Electronic Devices ◽  
Electronic Switches

An efficient way to reduce the power consumption of electronic devices is to lower the supply voltage, but this voltage is restricted by the thermionic limit of subthreshold swing (SS), 60 millivolts per decade, in field-effect transistors (FETs). We show that a graphene Dirac source (DS) with a much narrower electron density distribution around the Fermi level than that of conventional FETs can lower SS. A DS-FET with a carbon nanotube channel provided an average SS of 40 millivolts per decade over four decades of current at room temperature and high device current I60 of up to 40 microamperes per micrometer at 60 millivolts per decade. When compared with state-of-the-art silicon 14-nanometer node FETs, a similar on-state current Ion is realized but at a much lower supply voltage of 0.5 volts (versus 0.7 volts for silicon) and a much steeper SS below 35 millivolts per decade in the off-state.

scholarly journals A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator

Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 223 ◽  
Author(s):  
Yannan Zhang ◽  
Ke Han ◽  
and Jiawei Li
Keyword(s):  
Metal Oxide ◽  
Low Power ◽  
Energy Efficient ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Future Generation ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Ultra Low Power

Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and faster devices, researchers and scientists have worked out a number of ways to further lower the leaking current of MOSFETs (Metal oxide semiconductor field effect transistor). Nanowire structure is now regarded as a promising candidate of future generation of logical devices due to its ultra-low off-state leaking current compares to FinFET. However, the potential of nanowire in terms of off-state current has not been fully discovered. In this article, a novel Core–Insulator Gate-All-Around (CIGAA) nanowire has been proposed, investigated, and simulated comprehensively and systematically based on 3D numerical simulation. Comparisons are carried out between GAA and CIGAA. The new CIGAA structure exhibits low off-state current compares to that of GAA, making it a suitable candidate of future low-power and energy-efficient devices.

scholarly journals Temperature Dependence of Dielectric Properties of Ferroelectric Heterostructures with Domain-Provided Negative Capacitance

Nanomaterials ◽  
2021 ◽  
Vol 12 (1) ◽  
pp. 75
Author(s):  
Maksim A. Pavlenko ◽  
Yuri A. Tikhonov ◽  
Anna G. Razumnaya ◽  
Valerii M. Vinokur ◽  
Igor A. Lukyanchuk
Keyword(s):  
Phase Diagram ◽  
Dielectric Properties ◽  
Temperature Dependence ◽  
Energy Efficient ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Negative Capacitance ◽  
Temperature Dependent ◽  
Domain Structures ◽  
Temperature Dependent Properties

It is well known that the ferroelectric layers in dielectric/ferroelectric/dielectric heterostructures harbor polarization domains resulting in the negative capacitance crucial for manufacturing energy-efficient field-effect transistors. However, the temperature behavior of the characteristic dielectric properties, and, hence, the corresponding behavior of the negative capacitance, are still poorly understood, restraining the technological progress thereof. Here we investigate the temperature-dependent properties of domain structures in the SrTiO3/PbTiO3/SrTiO3 heterostructures and demonstrate that the temperature–thickness phase diagram of the system includes the ferroelectric and paraelectric regions, which exhibit different responses to the applied electric field. Using phase-field modeling and analytical calculations we find the temperature dependence of the dielectric constant of ferroelectric layers and identify the regions of the phase diagram wherein the system demonstrates negative capacitance. We further discuss the optimal routes for implementing negative capacitance in energy-efficient ferroelectric field-effect transistors.

Energy‐Efficient Metal–Insulator–Metal‐Semiconductor Field‐Effect Transistors Based on 2D Carrier Gases

2019 ◽  
Vol 5 (5) ◽  
pp. 1800832 ◽  
Author(s):  
Meiyong Liao ◽  
Liwen Sang ◽  
Takehiro Shimaoka ◽  
Masataka Imura ◽  
Satoshi Koizumi ◽  
...  
Keyword(s):  
Energy Efficient ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Metal Insulator ◽  
Metal Insulator Metal ◽  
Carrier Gases

scholarly journals Design and Analysis of CMOS and CNTFET based Ternary Operators for Scrambling

2019 ◽  
Vol 4 (5) ◽  
pp. 575-579
Author(s):  
Gudala Konica . ◽  
Sreenivasulu Mamilla .
Keyword(s):  
Energy Efficient ◽  
Field Effect ◽  
High Performance ◽  
Digital Circuits ◽  
Performance Metrics ◽  
Supply Voltage ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Future Generations ◽  
Power Delay Product

As silicon technology scales down, it is a dominant choice to have high-performance digital circuits. As researchers investigated for high-performance digital circuits for future generations, Carbon Nanotube Field Effect Transistors (CNTFETs) is considered as the most promising technology due to their excellent current driving capability and proved to be an alternative to conventional CMOS technology. A CNTFET based energy efficient ternary operators are proposed for scrambling applications. The transistor-level implementations of operators namely Scrambling Operator1 (SOP1), Scrambling Operator2 (SOP2) and SUM operators are simulated with CMOS and CNTFET in 32 nm technology at 0.9 V supply voltage using Synopsys HSPICE. The performance metrics like Power, Delay and Power-delay product (PDP) are measured and a comparative analysis for CNTFET and CMOS technologies is carried out. The results demonstrate that CNTFET designs have better-optimized results in power, energy consumption, and reduced transistor count.

Energy-efficient, fully flexible, high-performance tactile sensor based on piezotronic effect: Piezoelectric signal amplified with organic field-effect transistors

Nano Energy ◽  
2020 ◽  
Vol 76 ◽  
pp. 105050 ◽  
Author(s):  
Jian Wang ◽  
Jianfeng Jiang ◽  
Congcong Zhang ◽  
Mingyuan Sun ◽  
Shuwei Han ◽  
...  
Keyword(s):  
Energy Efficient ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Tactile Sensor ◽  
Organic Field Effect Transistors ◽  
Piezotronic Effect
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