Radiation hard circuit design: flip-flop and SRAM

2019 ◽  
pp. 249-278 ◽  
Keyword(s):  
Circuit Design ◽  
Flip Flop ◽  
Radiation Hard

A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect

2013 ◽  
Vol E96.C (4) ◽  
pp. 511-517 ◽  
Author(s):  
Kuiyuan ZHANG ◽  
Jun FURUTA ◽  
Ryosuke YAMAMOTO ◽  
Kazutoshi KOBAYASHI ◽  
Hidetoshi ONODERA
Keyword(s):  
Flip Flop ◽  
Multiple Cell ◽  
Radiation Hard

An Area-Efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets

2011 ◽  
Vol 58 (6) ◽  
pp. 3053-3059 ◽  
Author(s):  
Ryosuke Yamamoto ◽  
Chikara Hamanaka ◽  
Jun Furuta ◽  
Kazutoshi Kobayashi ◽  
Hidetoshi Onodera
Keyword(s):  
Flip Flop ◽  
Multiple Cell ◽  
Radiation Hard ◽  
Area Efficient

Design and Implementation of QCA D-Flip-Flops and RAM Cell Using Majority Gates

2019 ◽  
Vol 28 (05) ◽  
pp. 1950079 ◽  
Author(s):  
Trailokya Nath Sasamal ◽  
Ashutosh Kumar Singh ◽  
Umesh Ghanekar
Keyword(s):  
Circuit Design ◽  
High Speed ◽  
High Performance ◽  
Single Layer ◽  
Memory Cell ◽  
Design Parameters ◽  
Flip Flop ◽  
Negative Edge ◽  
Wire Crossing ◽  
The Common

Quantum-dot cellular automata (QCA) is one of the promising technologies that enable nanoscale circuit design with high performance and low-power consumption features. As memory cell and flip-flops are rudimentary for most of the digital circuits, having a high speed, and a less complex memory cell is significantly important. This paper presents novel architecture of D flip-flops and memory cell using a recently proposed five-input majority gate in QCA technology and simulated by QCADesigner tool version 2.0.3. The simulation results show that the proposed D flip-flops and the memory cell are more superior to the existing designs by considering the common design parameters. The proposed RAM cell spreads over an area of 0.12[Formula: see text][Formula: see text]m2and delay of 1.5 clock cycles. The proposed level-triggered, positive/negative edge-triggered, and dual edge-triggered D flip-flop uses 14%, 33%, and 21% less area, whereas the latency is 40%, 27%, and 25% less when compared to the previous best design. In addition, all the proposed designs are implemented in a single layer QCA and do not require any single or multilayer wire crossing.

A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop, DICE ACFF, in a 65 nm Thin-BOX FD-SOI

2014 ◽  
Vol 61 (4) ◽  
pp. 1881-1888 ◽  
Author(s):  
K. Kobayashi ◽  
K. Kubota ◽  
M. Masuda ◽  
Y. Manzawa ◽  
J. Furuta ◽  
...  
Keyword(s):  
Low Power ◽  
Flip Flop ◽  
Radiation Hard ◽  
Area Efficient

SINUSOIDAL CLOCKED SENSE-AMPLIFIER-BASED ENERGY RECOVERY FLIP-FLOPS

2014 ◽  
Vol 23 (05) ◽  
pp. 1450066
Author(s):  
JITENDRA KANUNGO ◽  
S. DASGUPTA
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Energy Recovery ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Sense Amplifier ◽  
Simulation Based ◽  
Digital Circuit Design

Energy recovery clocking is an ultimate solution to the ultra low power sequential digital circuit design. In this paper, we present a new slave latch for a sense-amplifier based flip-flop (SAFF). Energy recovery sinusoidal clock is applied to the low power SAFF. Extensive simulation based comparisons among reported and proposed SAFF are carried-out at 90 nm CMOS technology node. The proposed flip-flop operating with energy recovery single phase sinusoidal clock shows better performance. The proposed flip-flop also reduces the leakage current and glitch.

The InP-HEMT IC Technology for 40-Gbit/s Optical Communications

2003 ◽  
Vol 13 (01) ◽  
pp. 141-173
Author(s):  
YASURO YAMANE ◽  
KOICHI MURATA
Keyword(s):  
Circuit Design ◽  
Communication Systems ◽  
High Speed ◽  
Optical Fiber Communication ◽  
High Yield ◽  
Passive Component ◽  
Fabrication Technology ◽  
Flip Flop ◽  
Ic Technology ◽  
Inp Hemt

We present the outline of the InP HEMT IC technology. This technology realizes InP HEMT digital ICs for 40-Gbit/s optical fiber communication systems through the integration of 0.1-μm-gate-length HEMTs, vertical diodes, capacitors, and WSiN resistors with two level interconnections. This paper describes the high-speed digital IC circuit design and fabrication in InP HEMT technology for 40-Gbit/s/channel optical communication systems. Some results on InP HEMTs' reliability are also covered. Basic circuit design techniques utilizing SCFL topology and fundamental circuit elements of the selector and D-type flip-flop are discussed in detail. The basic digital ICs of MUX, D-FF, and DEMUX ICs fabricated with 0.1-μm-gate InP HEMTs successfully operated up to 50 Gbit/s in the packaged modules. These IC modules offer large speed margins for the 43-Gbit/s OTU-3 data rate. In order to develop cost-effective optical transmitters and receivers, we designed a PLL-based CDR with a full-rate architecture. The fully monolithic integrated CDR exhibited error-free operation for 231-1 PRBS data signal at the OTU-3 bit rate of 43.0184 Gbit/s. Four-bit MUX and DEMUX ICs are other key components, and could be implemented by using InP HEMT technology. Additionally, we describe InP-IC fabrication technology with two-level inter-connection. This is already fully matured for 40-Gbit/s SSI fabrication. The uniform FET characteristics and high-yield passive component fabrication technologies support this degree of maturity. InP HEMT lifetime is 107 hours at l00°C. These results prove the InP HEMT IC fabrication technology presented here, to be highly reliable. These investigation show that robust performance and yield when realizing SSI and MSI 40-Gbit/s functions.

Selective Flip-Flop Optimization for Reliable Digital Circuit Design

2020 ◽  
Vol 39 (7) ◽  
pp. 1484-1497 ◽  
Author(s):  
Mohammad Saber Golanbari ◽  
Saman Kiamehr ◽  
Mojtaba Ebrahimi ◽  
Mehdi B. Tahoori
Keyword(s):  
Circuit Design ◽  
Digital Circuit ◽  
Flip Flop ◽  
Digital Circuit Design
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