scholarly journals LDPC Decoder of High Speed Multi-Rate DVB-S2 Based on FPGA

2019 ◽  
Vol 37 (2) ◽  
pp. 299-307 ◽  
Author(s):  
TianJiao Xie ◽  
Bo Li ◽  
Mao Yang ◽  
Zhongjiang Yan
Keyword(s):  
High Speed ◽  
State Of The Art ◽  
Ldpc Codes ◽  
The State ◽  
Elementary Transformation ◽  
Parity Check ◽  
Ldpc Decoder ◽  
Art Works ◽  
Decoder Architecture ◽  
Lower Triangular

A multi-rate LDPC decoder architecture for DVB-S2 codes based on FPGA is proposed. Through elementary transformation on the parity check matrices of DVB-S2 LDPC codes, a new matrix whose left is a QC sub-matrix and right is Transformation of Staircase lower triangular (TST) sub-matrix is obtained. The QC and TST are designed separately, therefore the successful experience of the most popular Quasi-Cyclic (QC) LDPC decoder architecture can be drawn on. While for TST sub-matrix, the variable nodes updating only need to be considered and the check nodes updating is realized compatibility with QC sub-matrix. Based on the proposed architectures, a multi-rate LDPC decoder implemented on Xilinx XC7VX485T FPGA can achieve the maximum decoding throughput of 2.5 Gbit/s at the 20 iterations when the operating frequency is 250 MHz, which demonstrates the highest throughput compared with the state-of-the-art works.

Implementation of Decoder for Effective Quasi-Cyclic LDPC Codes Based on FPGA

2013 ◽  
Vol 791-793 ◽  
pp. 1867-1871
Author(s):  
Ji Qu Han ◽  
Li Liu
Keyword(s):  
High Speed ◽  
Ldpc Codes ◽  
Parity Check ◽  
Decoding Algorithm ◽  
Parity Check Matrix ◽  
Throughput Rate ◽  
Triangular Structure ◽  
Check Matrix ◽  
Decoder Architecture ◽  
Lower Triangular

Designers are increasingly relying on FPGA-based emulation to evaluate the performance of LDPC codes. In this paper, we propose a novel approximate lower triangular structure for the parity part of the parity-check matrix of QC-LDPC codes. Next, a high speed partially parallel decoder architecture which based on the Offset BP-based decoding algorithm is proposed. The results indicate that the frequency can reach 100MHz and its throughput rate can reach 113Mbps.

An Efficient VLSI Architecture for Nonbinary LDPC Decoder with Adaptive Message Control

2015 ◽  
Vol 4 (1) ◽  
pp. 6
Author(s):  
Varatharajan Ramachandran
Keyword(s):  
Power Consumption ◽  
Vlsi Architecture ◽  
Ldpc Codes ◽  
Parity Check ◽  
Decoding Complexity ◽  
Ldpc Decoder ◽  
Message Length ◽  
Low Density Parity Check ◽  
Decoder Architecture ◽  
Memory Accesses

<p>A new decoder architecture for nonbinary low-density parity check (LDPC) codes is presented in this paper to reduce the hardware operational complexity and power consumption. Adaptive message control (AMC) is to achieve the low decoding complexity,  that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. A new horizontal nonbinary LDPC decoder architecture is developed to implement AMC. Key components in the architecture have been designed with the consideration of variable message lengths to leverage the benefit of the proposed AMC. Simulation results demonstrate that the proposed nonbinary LDPC decoder architecture can significantly reduce hardware operations and power consumption as compared with existing work with negligible performance degradation.</p>

scholarly journals A novel error correction protocol for continuous variable quantum key distribution

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Kadir Gümüş ◽  
Tobias A. Eriksson ◽  
Masahiro Takeoka ◽  
Mikio Fujiwara ◽  
Masahide Sasaki ◽  
...  
Keyword(s):  
Error Correction ◽  
Quantum Key Distribution ◽  
Ldpc Codes ◽  
Key Distribution ◽  
Continuous Variable ◽  
Early Termination ◽  
Parity Check ◽  
Secret Key ◽  
Ldpc Decoder ◽  
And Performance

AbstractReconciliation is a key element of continuous-variable quantum key distribution (CV-QKD) protocols, affecting both the complexity and performance of the entire system. During the reconciliation protocol, error correction is typically performed using low-density parity-check (LDPC) codes with a single decoding attempt. In this paper, we propose a modification to a conventional reconciliation protocol used in four-state protocol CV-QKD systems called the multiple decoding attempts (MDA) protocol. MDA uses multiple decoding attempts with LDPC codes, each attempt having fewer decoding iteration than the conventional protocol. Between each decoding attempt we propose to reveal information bits, which effectively lowers the code rate. MDA is shown to outperform the conventional protocol in regards to the secret key rate (SKR). A 10% decrease in frame error rate and an 8.5% increase in SKR are reported in this paper. A simple early termination for the LDPC decoder is also proposed and implemented. With early termination, MDA has decoding complexity similar to the conventional protocol while having an improved SKR.

Accelerating Mobile-Cloud Computing

2015 ◽  
pp. 1933-1955
Author(s):  
Tolga Soyata ◽  
He Ba ◽  
Wendi Heinzelman ◽  
Minseok Kwon ◽  
Jiye Shi
Keyword(s):  
Cloud Computing ◽  
Mobile Devices ◽  
High Speed ◽  
Mobile Cloud Computing ◽  
Response Times ◽  
State Of The Art ◽  
The State ◽  
Mobile Cloud ◽  
Computational Resources ◽  
Traditional Approaches

With the recent advances in cloud computing and the capabilities of mobile devices, the state-of-the-art of mobile computing is at an inflection point, where compute-intensive applications can now run on today's mobile devices with limited computational capabilities. This is achieved by using the communications capabilities of mobile devices to establish high-speed connections to vast computational resources located in the cloud. While the execution scheme based on this mobile-cloud collaboration opens the door to many applications that can tolerate response times on the order of seconds and minutes, it proves to be an inadequate platform for running applications demanding real-time response within a fraction of a second. In this chapter, the authors describe the state-of-the-art in mobile-cloud computing as well as the challenges faced by traditional approaches in terms of their latency and energy efficiency. They also introduce the use of cloudlets as an approach for extending the utility of mobile-cloud computing by providing compute and storage resources accessible at the edge of the network, both for end processing of applications as well as for managing the distribution of applications to other distributed compute resources.

scholarly journals Lossless Image Compression Techniques: A State-of-the-Art Survey

Symmetry ◽  
2019 ◽  
Vol 11 (10) ◽  
pp. 1274 ◽  
Author(s):  
Md. Atiqur Rahman ◽  
Mohamed Hamada
Keyword(s):  
Image Compression ◽  
High Speed ◽  
Communication Theory ◽  
State Of The Art ◽  
Signal To Noise Ratio ◽  
Daily Basis ◽  
The State ◽  
Huge Amount ◽  
Lossless Image Compression ◽  
Art Techniques

Modern daily life activities result in a huge amount of data, which creates a big challenge for storing and communicating them. As an example, hospitals produce a huge amount of data on a daily basis, which makes a big challenge to store it in a limited storage or to communicate them through the restricted bandwidth over the Internet. Therefore, there is an increasing demand for more research in data compression and communication theory to deal with such challenges. Such research responds to the requirements of data transmission at high speed over networks. In this paper, we focus on deep analysis of the most common techniques in image compression. We present a detailed analysis of run-length, entropy and dictionary based lossless image compression algorithms with a common numeric example for a clear comparison. Following that, the state-of-the-art techniques are discussed based on some bench-marked images. Finally, we use standard metrics such as average code length (ACL), compression ratio (CR), pick signal-to-noise ratio (PSNR), efficiency, encoding time (ET) and decoding time (DT) in order to measure the performance of the state-of-the-art techniques.

Learning deep optimizer for blind image deconvolution

2019 ◽  
Vol 17 (06) ◽  
pp. 1950044
Author(s):  
Zhijian Luo ◽  
Siyu Chen ◽  
Yuntao Qian
Keyword(s):  
Simple Form ◽  
State Of The Art ◽  
Solution Space ◽  
The State ◽  
Image Deconvolution ◽  
Competitive Performance ◽  
Propagation Behavior ◽  
Art Works ◽  
Blind Image Deconvolution ◽  
Blind Image

In blind image deconvolution, priors are often leveraged to constrain the solution space, so as to alleviate the under-determinacy. Priors which are trained separately from the task of deconvolution tend to be unstable. We propose the Golf Optimizer, a novel but simple form of network that learns deep priors from data with better propagation behavior. Like playing golf, our method first estimates an aggressive propagation towards optimum using one network, and recurrently applies a residual CNN to learn the gradient of prior for delicate correction on restoration. Experiments show that our network achieves competitive performance on GoPro dataset, and our model is extremely lightweight compared with the state-of-the-art works.

High-Speed and Area-Efficient Reconfigurable Multiplexer Bank for RAM-Based Finite State Machine Implementations

2015 ◽  
Vol 24 (07) ◽  
pp. 1550101 ◽  
Author(s):  
Raouf Senhadji-Navaro ◽  
Ignacio Garcia-Vargas
Keyword(s):  
High Speed ◽  
Finite State Machine ◽  
State Of The Art ◽  
Behavioral Model ◽  
State Machine ◽  
The State ◽  
Experimental Results ◽  
State Machines ◽  
Finite State ◽  
Area Efficient

This work is focused on the problem of designing efficient reconfigurable multiplexer banks for RAM-based implementations of reconfigurable state machines. We propose a new architecture (called combination-based reconfigurable multiplexer bank, CRMUX) that use multiplexers simpler than that of the state-of-the-art architecture (called variation-based reconfigurable multiplexer bank, VRMUX). The performance (in terms of speed, area and reconfiguration cost) of both architectures is compared. Experimental results from MCNC finite state machine (FSM) benchmarks show that CRMUX is faster and more area-efficient than VRMUX. The reconfiguration cost of both multiplexer banks is studied using a behavioral model of a reconfigurable state machine. The results show that the reconfiguration cost of CRMUX is lower than that of VRMUX in most cases.

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