Micromagnetic studies of domain structures and switching properties in a magnetoresistive random access memory cell

2005 ◽  
Vol 97 (10) ◽  
pp. 10E310 ◽  
Author(s):  
Guoguang Wu ◽  
Juan Yu ◽  
Fulin Wei ◽  
Xiaoxi Liu ◽  
Dan Wei
Keyword(s):  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Access Memory ◽  
Domain Structures ◽  
Magnetoresistive Random Access Memory

Nonvolatile Magnetoresistive Random-Access Memory Based on Magnetic Tunnel Junctions

MRS Bulletin ◽  
2004 ◽  
Vol 29 (11) ◽  
pp. 818-821 ◽  
Author(s):  
G. Grynkewich ◽  
J. Åkerman ◽  
P. Brown ◽  
B. Butcher ◽  
R.W. Dave ◽  
...  
Keyword(s):  
Flash Memory ◽  
High Speed ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Memory Cell ◽  
Random Access Memory ◽  
Access Memory ◽  
Magnetoresistive Random Access Memory ◽  
Static Ram ◽  
New Memory Technology

AbstractMagnetoresistive random-access memory (MRAM) is a new memory technology that is nearing commercialization. MRAM integrates a magnetic tunnel junction (MTJ) device with standard silicon-based microelectronics, resulting in a combination of qualities not found in other memory technologies. For example, MRAM is nonvolatile, has unlimited read and write endurance, and is capable of high-speed read and write operations. In this article, we will describe the fundamentals of an MTJ-based MRAM as well as recent important technology developments in the areas of magnetic materials and memory cell architecture. In addition, we will compare the present and future capabilities of MRAM to those of existing memory technologies such as static RAM and flash memory.

Submicron spin valve magnetoresistive random access memory cell

1997 ◽  
Vol 81 (8) ◽  
pp. 3992-3994 ◽  
Author(s):  
E. Y. Chen ◽  
S. Tehrani ◽  
T. Zhu ◽  
M. Durlam ◽  
H. Goronkin
Keyword(s):  
Spin Valve ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Access Memory ◽  
Magnetoresistive Random Access Memory

scholarly journals Pre-Emphasis Pulse Design for Random-Access Memory

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1454
Author(s):  
Yoshihiro Sugiura ◽  
Toru Tanzawa
Keyword(s):  
Time Constant ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Memory Access ◽  
Access Time ◽  
Access Memory ◽  
Delay Times ◽  
Cell Current ◽  
The Impact

This paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact of the process variation in the time constant of WL, the cell current, and the resistance of deciding path on optimum PE pulses are discussed. Optimum PE pulse widths and resultant minimum WL delay times are modeled with fitting curves as a function of column address of the accessed memory cell, which provides designers with the ability to set the optimum timing for WL and BL (bit-line) operations, reducing average memory access time.

Temperature Dependence of Phase-Change Random Access Memory Cell

2006 ◽  
Vol 45 (5A) ◽  
pp. 3955-3958 ◽  
Author(s):  
X. S. Miao ◽  
L. P. Shi ◽  
H. K. Lee ◽  
J. M. Li ◽  
R. Zhao ◽  
...  
Keyword(s):  
Phase Change ◽  
Temperature Dependence ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Access Memory

Magnetoelectric Assisted 180° Magnetization Switching for Electric Field Addressable Writing in Magnetoresistive Random-Access Memory

ACS Nano ◽  
2014 ◽  
Vol 8 (8) ◽  
pp. 7793-7800 ◽  
Author(s):  
Zhiguang Wang ◽  
Yue Zhang ◽  
Yaojin Wang ◽  
Yanxi Li ◽  
Haosu Luo ◽  
...  
Keyword(s):  
Electric Field ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Magnetization Switching ◽  
Magnetoresistive Random Access Memory

A Novel Peripheral Circuit for SWSFET Based Multivalued Static Random-Access Memory

2020 ◽  
Vol 29 (01n04) ◽  
pp. 2040010
Author(s):  
R. H. Gudlavalleti ◽  
B. Saman ◽  
R. Mays ◽  
Evan Heller ◽  
J. Chandy ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Quantum Well ◽  
Field Effect Transistors ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Input Gate ◽  
Reduction In Area

This paper presents the peripheral circuitry for a multivalued static random-access memory (SRAM) based on 2-bit CMOS cross-coupled inverters using spatial wavefunction switched (SWS) field effect transistors (SWSFETs). The novel feature is a two quantum well/quantum dot channel n-SWSFET access transistor. The reduction in area with four-bit storage-per-cell increases the memory density and efficiency of the SRAM array. The SWSFET has vertically stacked two-quantum well/quantum dot channels between the source and drain regions. The upper or lower quantum charge locations in the channel region is based on the input gate voltage. The analog behavioral modeling (ABM) of the SWSFET device is done using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit simulations for the proposed memory cell and addressing/peripheral circuitry are presented.

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