Benefits of Zero Degree Single Wafer High Energy Implants for Advanced Semiconductor Device Fabrication

2008 ◽  
Author(s):  
Woojin Lee ◽  
Thirumal Thanigaivelan ◽  
Hans-Joachim Gossmann ◽  
Russell Low ◽  
Benjamin Colombeau ◽  
...  
Keyword(s):  
Semiconductor Device ◽  
High Energy ◽  
Device Fabrication ◽  
Zero Degree

Irradiation Induced Changes in Semiconducting Thin Films

2013 ◽  
Vol 341 ◽  
pp. 181-210 ◽  
Author(s):  
S.K. Tripathi
Keyword(s):  
Thin Films ◽  
Solar Cells ◽  
Heavy Ions ◽  
Semiconductor Device ◽  
High Energy ◽  
Device Fabrication ◽  
Electrical Performance ◽  
Radiation Environment ◽  
Extended Defects ◽  
Semiconducting Thin Films

High-energy electron, proton, neutron, photon and ion irradiation of semiconductor diodes and solar cells has long been a topic of considerable interest in the field of semiconductor device fabrication. The inevitable damage production during the process of irradiation is used to study and engineer the defects in semiconductors. In a strong radiation environment in space, the electrical performance of solar cells is degraded due to direct exposure to energetically charged particles. A considerable amount of work has been reported on the study of radiation damage in various solar cell materials and devices in the recent past. In most cases, high-energy heavy ions damage the material by producing a large amount of extended defects, but high-energy light ions are suitable for producing and modifying the intrinsic point defects. The defects can play a variety of electronically active roles that affect the electrical, structural and optical properties of a semiconductor. This review article aims to present an overview of the advancement of research in the modification of glassy semiconducting thin films using different types of radiations (light, proton and swift heavy ions). The work which has been done in our laboratory related to irradiation induced effects in semiconducting thin films will also be compared with the existing literature.

Semiconductor Device Fabrication with High Energy Ion Implantation

ESSDERC ’89 ◽  
1989 ◽  
pp. 33-36
Author(s):  
T. Harms ◽  
K. Goser ◽  
U. Hilleringmann ◽  
W. Fahrner ◽  
K. Oppermann
Keyword(s):  
Ion Implantation ◽  
Semiconductor Device ◽  
High Energy ◽  
Device Fabrication

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

Innovative Curriculum on Electronic Materials Processing and Engingeering

2001 ◽  
Vol 684 ◽  
Author(s):  
Jane P. Chang
Keyword(s):  
Semiconductor Manufacturing ◽  
Chemical Engineering ◽  
Materials Science ◽  
Semiconductor Device ◽  
Electronic Materials ◽  
Dynamic Environment ◽  
Complementary Metal Oxide Semiconductor ◽  
Device Fabrication ◽  
Oxide Semiconductor ◽  
Solid State Physics

Recognizing that the traditional engineering education training is often inadequate in preparing the students for the challanges presented by this industry's dynamic environment and insufficient to meet the empoyer's criteria in hiring new engineers, a new curriculum on Semiconductor Manufacturing is instituted in the Chemical Engineering Department at UCLA to train the students in various scientific and technologica areas that are pertinenet to the microelectronics industries. This paper describes this new mutidisciplinary curriculum that provides knowledge and skills in semiconductor manufacturing through a series ofcourses that emphasize on the application of fundamenta engineeering disciplines in solid-state physics, materials science of semiconductors, and chemical processing. The curriculum comprises three major components:(1)a comprehensive course curriculum in semiconductor manufacturing; (2) a laboratory for hands-on training in semiconductor device fabrication; (3) design of experiments. The capstone laboratory course is designed to strengthen students’ training in “unit operatins” used in semicounductor manufacturing and allow them to practice engineering principles using the state-of-the-art experimental setup. It comprises the most comprehensive training(seven photolithographic steps and numero0us chemical processes)in fabricating and testing complementary metal-oxide-semiconductor (CMOS) devices. This curriculum is recentyaccredited by the Accreditation Board for Engineering and Technology(ABET).

Mapping of Process-Induced Dopant Redistributions by Electron Holography

2004 ◽  
Vol 10 (4) ◽  
pp. 462-469 ◽  
Author(s):  
Wolf-Dieter Rau ◽  
Alexander Orchowski
Keyword(s):  
Semiconductor Device ◽  
Device Fabrication ◽  
Electron Holography ◽  
Dopant Diffusion ◽  
Fundamental Parameters ◽  
Device Processing ◽  
Device Structures ◽  
Before And After ◽  
Potential Applications ◽  
Junction Potential

We present and review dopant mapping examples in semiconductor device structures by electron holography and outline their potential applications for experimental investigation of two-dimensional (2D) dopant diffusion on the nanometer scale. We address the technical challenges of the method when applied to transistor structures with respect to quantification of the results in terms of the 2Dp–njunction potential and critically review experimental boundary conditions, accuracy, and potential pitfalls. By obtaining maps of the inner electrostatic potential before and after anneals typically used in device processing, we demonstrate how the “vertical” and “lateral” redistribution of boron during device fabrication can directly be revealed. Such data can be compared with the results of process simulation to extract the fundamental parameters for dopant diffusion in complex device structures.

Infrared Emission Spectra of Indium Phosphide at Elevated Temperatures

1997 ◽  
Vol 502 ◽  
Author(s):  
H. Rogne ◽  
P. J. Timans ◽  
H. Ahmed
Keyword(s):  
Elevated Temperatures ◽  
Semiconductor Device ◽  
Thermal Emission ◽  
Emission Spectra ◽  
Infrared Emission ◽  
Device Fabrication ◽  
Optical Measurements ◽  
Optical Data ◽  
Monitoring And Control ◽  
Process Monitoring And Control

ABSTRACTProcess monitoring and control during semiconductor device fabrication frequently relies on good knowledge of the optical properties of the substrate wafer and the surface coatings. However, these optical data are often unavailable, and as a consequence errors arise in pyrometric temperature measurements, as well as in thermal modelling of heating cycles. In this study, isothermal electron beam heating has been combined with in situ optical measurements to record thermal emission spectra of undoped InP specimens from 347 to 478°C, at wavelengths between I and 9 μm. The absorption coefficient was deduced from the emission spectra and reveals information about the temperature dependence of the infrared absorption mechanisms in InP.

Silicon-on-SiC, a Novel Semiconductor Structure for Power Devices

2010 ◽  
Vol 645-648 ◽  
pp. 1243-1246 ◽  
Author(s):  
Michael R. Jennings ◽  
Amador Pérez-Tomás ◽  
Owen J. Guy ◽  
Michal Lodzinski ◽  
Peter M. Gammon ◽  
...  
Keyword(s):  
Thermal Oxidation ◽  
Smooth Surface ◽  
Semiconductor Device ◽  
Device Fabrication ◽  
Layer Transfer ◽  
Power Devices ◽  
Bonding Quality ◽  
Afm Analysis ◽  
Electrical Analysis ◽  
Density Of Interface States

A physical and electrical analysis of Si/SiC heterojunctions formed by layer transfer based on the smartcut® process is presented in this paper. AFM and SEM have revealed a high bonding quality when Si wafers are transferred to SiC on-axis wafers. XRD points to the fact that the layers are monocrystalline in nature. A surface AFM analysis of the bonded wafers demonstrated a smooth surface (rms = 5.8 nm) suitable for semiconductor device fabrication. Capacitors have been fabricated from the Si/SiC heterojunctions, which have been totally oxidised. Oxidised Si/SiC structures yielded a lower density of interface states than conventional thermal oxidation techniques.

Stress in Titanium Disilicide Layers, During and After Formation.

1988 ◽  
Vol 130 ◽  
Author(s):  
J. F. Jongste ◽  
F. E. Prins ◽  
G. C. A. M. Janssen ◽  
S. Radelaar
Keyword(s):  
Silicon Substrate ◽  
Semiconductor Device ◽  
Linear Thermal Expansion ◽  
Deposition Process ◽  
Device Fabrication ◽  
Titanium Disilicide ◽  
Titanium Layer ◽  
Thermal Expansion Coefficients ◽  
The Difference ◽  
Interconnect Lines

AbstractDuring and after formation of a thin layer of titanium disilicide (TiSi2) on a silicon substrate stress is caused in several ways: Intrinsic stresses are due to the deposition process or to phase transformations and grain growth of the deposited material. Extrinsic stresses are caused by thermal effects: the difference in linear thermal expansion coefficients of the layer and the substrate respectively. Problems related to stresses can occur in semiconductor device fabrication. Stresses can deteriorate gate oxides in MOSFETs and can cause cracks in interconnect lines. Also, focusing problems in lithographic steps can occur because of wafer warpage. In this paper some examples of the different types of stress that can occur are shown and discussed. Both multilayer and self aligned Ti-Si samples have been studied: The advantage of the use of Ti-Si multilayers to produce TiSi2 is that diffusion has to proceed only over a short distance i.e., the multilayer period. So the annealing time can be short. In the self aligned silicidation process, where a layer of a titanium layer on top of a silicon substrate is annealed, the diffusion length is equal to the thickness of the Ti layer. Because longer annealing times are needed, the latter type is used to monitor stress during formation.

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