scholarly journals Statistical metrology—measurement and modeling of variation for advanced process development and design rule generation

1998 ◽  
Author(s):  
Duane S. Boning ◽  
James E. Chung
Keyword(s):  
Process Development ◽  
Design Rule ◽  
Rule Generation

Failure Types & Analysis In Cu Process Development of Design-Rule 0.18μm CPU

2001 ◽  
Author(s):  
DongKwon Jeong ◽  
JuHyeon Ahn ◽  
SangIn Lee ◽  
JooHyuk Chung ◽  
ByungLyul Park ◽  
...  
Keyword(s):  
Process Improvement ◽  
Process Development ◽  
Metal Corrosion ◽  
Pass Rate ◽  
Design Rule ◽  
The Novel ◽  
Corrosion Loss ◽  
Barrier Metal ◽  
Development State ◽  
Failure Types

Abstract This paper presents the problems, the solutions, and the development state of the novel 0.18 μm Cu Metal Process through failure analysis of the Alpha CPU under development at Samsung Electronics. The presented problems include : “Via Bottom Lifting” induced by the Cu Via void, “Via Bottom dissociation” due to the IMD stress, “Via side dissociation” due to the poor formation of the Barrier Metal, “Via short/not-open failure” due to the IMD lifting, and Cu metal Corrosion/Loss. The analysis was carried out on the Via Contact Test Chain Patterns, using the “Electron (ION) Charge Up” method. After carefully analyzing each of the failure types, process improvement efforts followed. As a result, the pass rate of the via contact Rc was brought up from a mere 20% to 95%, and the device speed higher than 1.1 GHz was achieved, which surpasses the target speed of 1 GHz.

scholarly journals Study for plasma etching of dielectric film in semiconductor device manufacturing. Review of ASET research project

2002 ◽  
Vol 74 (3) ◽  
pp. 381-395 ◽  
Author(s):  
Makoto Sekine
Keyword(s):  
Plasma Etching ◽  
Semiconductor Device ◽  
Process Development ◽  
Reaction Model ◽  
Design Rule ◽  
Plasma Etch ◽  
Electron Collisions ◽  
Ion Energy ◽  
Etched Surface ◽  
Polymer Thickness

Conventional developments were conducted in a very empirical way, such as a trial and error with many speculations using qualitative data. This approach requires more and more resources and time for the development of future devices with a design rule below 100 nm in the system on a chip (SOC) era. It is necessary to establish a systematic methodology for process development and qualification. ASET Plasma Laboratory had been found to research a basis for the systematic development of the plasma etching technology. Fluorocarbon (CF) plasma for the etching of high-aspect-ratio contact holes in SiO2 was investigated intensively in the 5-year program that finished in March 2001. They introduced 5 plasma sources that can etch 0.1-mm contact holes on a 200-mm wafer in production, and state-of-the-art diagnostics tools for the plasma and etched surface. The SiO2 etch mechanism was revealed from the etch species generation to the reaction in a deep hole. The number of electron collisions to fluorocarbon gas molecule is proposed as an important parameter to control the gas dissociation and etch species flux to the surface. An etch reaction model was also proposed using the estimated-surface-reaction probability that is a function of ion energy and CF polymer thickness that reduces the net ion energy to the reaction layer. The CF polymer thickness was determined by a balance equation of generation term (radical fluxes) and loss terms (etching by ions, radicals, and out-flux oxygen from SiO2). A program was developed and successfully predicts the etch rates of Si-containing materials, including organic dielectrics. Requirements for the next-generation plasma etch tools are also discussed.

Advanced TEM sample preparation techniques for submicron Si devices

1995 ◽  
Vol 53 ◽  
pp. 516-517 ◽  
Author(s):  
P. B. Basham ◽  
H. L. Tsai
Keyword(s):  
Sample Preparation ◽  
Process Development ◽  
Light Transmission ◽  
Specific Area ◽  
Turnaround Time ◽  
Small Hole ◽  
Area Of Interest ◽  
Transmission Electron ◽  
Polished Side ◽  
Preparation Techniques

The use of transmission electron microscopy (TEM) to support process development of advanced microelectronic devices is often challenged by a large amount of samples submitted from wafer fabrication areas and specific-spot analysis. Improving the TEM sample preparation techniques for a fast turnaround time is critical in order to provide a timely support for customers and improve the utilization of TEM. For the specific-area sample preparation, a technique which can be easily prepared with the least amount of effort is preferred. For these reasons, we have developed several techniques which have greatly facilitated the TEM sample preparation.For specific-area analysis, the use of a copper grid with a small hole is found to be very useful. With this small-hole grid technique, TEM sample preparation can be proceeded by well-established conventional methods. The sample is first polished to the area of interest, which is then carefully positioned inside the hole. This polished side is placed against the grid by epoxy Fig. 1 is an optical image of a TEM cross-section after dimpling to light transmission.

The Structure and Properties of MoSi2 Thin Film in Mos Process

1980 ◽  
Vol 38 ◽  
pp. 326-327
Author(s):  
C.K. Wu ◽  
P. Chang ◽  
N. Godinho
Keyword(s):  
Thin Film ◽  
Integrated Circuits ◽  
High Performance ◽  
Large Scale ◽  
Process Development ◽  
Structure And Properties ◽  
Metal Silicides ◽  
High Oxidation ◽  
Important Approach ◽  
High Oxidation Resistance

Recently, the use of refractory metal silicides as low resistivity, high temperature and high oxidation resistance gate materials in large scale integrated circuits (LSI) has become an important approach in advanced MOS process development (1). This research is a systematic study on the structure and properties of molybdenum silicide thin film and its applicability to high performance LSI fabrication.

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