Novel modification in evanescent mode analysis to incorporate sub-1 nm equivalent oxide thickness in the subthreshold model of junctionless asymmetric double gate FETs

2020 ◽  
Vol 36 (1) ◽  
pp. 015007
Author(s):  
Ajit Kumar ◽  
J N Roy
Keyword(s):  
Oxide Thickness ◽  
Mode Analysis ◽  
Double Gate ◽  
Equivalent Oxide Thickness ◽  
Evanescent Mode

High-field mobility metal-gate/high-κ Ge n-MOSFETs with small equivalent-oxide-thickness

2011 ◽  
Vol 55 (1) ◽  
pp. 64-67 ◽  
Author(s):  
W.B. Chen ◽  
C.H. Cheng ◽  
C.W. Lin ◽  
P.C. Chen ◽  
Albert Chin
Keyword(s):  
High Field ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness ◽  
Metal Gate ◽  
Field Mobility

scholarly journals Subthreshold swing model using scale length for sub-10 nm junction-based double-gate MOSFETs

2020 ◽  
Vol 10 (2) ◽  
pp. 1747
Author(s):  
Hakkee Jung
Keyword(s):  
Analytical Model ◽  
Potential Distribution ◽  
Geometric Mean ◽  
Oxide Thickness ◽  
Channel Length ◽  
Subthreshold Swing ◽  
Double Gate ◽  
Silicon Thickness ◽  
The Relationship ◽  
Scale Length

We propose an analytical model for subthreshold swing using scale length for sub-10 nm double gate (DG) MOSFETs. When the order of the calculation for the series type potential distribution is increased it is possible to obtain accuracy, but there is a problem that the calculation becomes large. Using only the first order calculation of potential distribution, we derive the scale length λ1 and use it to obtain an analytical model of subthreshold swing. The findings show this subthreshold swing model is in concordance with a 2D simulation. The relationship between the channel length and silicon thickness, which can analyze the subthreshold swing using λ1, is derived by the relationship between the scale length and the geometric mean of the silicon and oxide thickness. If the silicon thickness and oxide film thickness satisfy the condition of (Lg-0.215)/6.38 > tsi(=tox), it is found that the result of this model agrees with the results using higher order calculations, within a 4% error range.

Current conduction of 0.72 nm equivalent-oxide-thickness LaO/HfO2 stacked gate dielectrics

2009 ◽  
Vol 95 (1) ◽  
pp. 012103 ◽  
Author(s):  
Chuan-Hsi Liu ◽  
Hung-Wen Chen ◽  
Shung-Yuan Chen ◽  
Heng-Sheng Huang ◽  
Li-Wei Cheng
Keyword(s):  
Gate Dielectrics ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness ◽  
Current Conduction

Sub-1 nm Equivalent Oxide Thickness Al-HfO2 Trapping Layer with Excellent Thermal Stability and Retention for Nonvolatile Memory

2018 ◽  
Vol 1 (9) ◽  
pp. 4633-4641 ◽  
Author(s):  
Sabina Spiga ◽  
Francesco Driussi ◽  
Gabriele Congedo ◽  
Claudia Wiemer ◽  
Alessio Lamperti ◽  
...  
Keyword(s):  
Thermal Stability ◽  
Nonvolatile Memory ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness ◽  
Excellent Thermal Stability
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