A novel multiple super junction power device structure with low specific on-resistance

2014 ◽  
Vol 35 (10) ◽  
pp. 104006 ◽  
Author(s):  
Hui Zhu ◽  
Haiou Li ◽  
Qi Li ◽  
Yuanhao Huang ◽  
Xiaoning Xu ◽  
...  
Keyword(s):  
Power Device ◽  
Device Structure

scholarly journals Simulation of a new hybrid Si/SiC power device for harsh environment applications

2015 ◽  
Vol 2015 (HiTEN) ◽  
pp. 000190-000194
Author(s):  
P.M. Gammon ◽  
C.W. Chan ◽  
P.A. Mawby
Keyword(s):  
Thin Film ◽  
High Temperature ◽  
Silicon On Insulator ◽  
Power Device ◽  
Harsh Environment ◽  
Silicon Thin Film ◽  
Device Structure ◽  
Solar Inverter ◽  
Thermal Simulations ◽  
Soi Substrates

A new power device structure is proposed, conceived to operate in a high temperature, harsh environment, for example within a motor drive application down hole, as an inverter in the engine bay of an electric car, or as a solar inverter in space. The lateral silicon power device resembles a laterally diffused MOSFET (LDMOS), such as those implemented within silicon on insulator (SOI) substrates. However, unlike SOI, the Si thin film has been transferred directly onto a semi-insulating 6H silicon carbide (6H-SiC) substrate via a wafer bonding process. Thermal simulations of the hybrid Si/SiC substrate have shown that the high thermal conductivity of the SiC will have a junction-to-case temperature approximately 4 times less that an equivalent SOI device, reducing the effects of self-heating. Electrical simulations of a 600 V power device, implemented entirely with the silicon thin film, suggest that it will retain the ability of SOI to minimise leakage at high temperature, but does so with 50% less conduction losses.

A new partial SOI power device structure with P-type buried layer

2005 ◽  
Vol 49 (12) ◽  
pp. 1965-1968 ◽  
Author(s):  
Baoxing Duan ◽  
Bo Zhang ◽  
Zhaoji Li
Keyword(s):  
Power Device ◽  
Device Structure ◽  
Buried Layer ◽  
P Type

High voltage silicon power device structure with substrate bias

2011 ◽  
Vol 47 (25) ◽  
pp. 1394-1396 ◽  
Author(s):  
Q. Li ◽  
X.M. Wei ◽  
W.D. Wang ◽  
H.O. Li
Keyword(s):  
High Voltage ◽  
Power Device ◽  
Substrate Bias ◽  
Device Structure

Influence of MBE Growth Conditions on Dislocation Densities of GaAs/Ge Epilayers Grown on Silicon Substrates

1985 ◽  
Vol 43 ◽  
pp. 364-365
Author(s):  
K.M. Hones ◽  
P. Sheldon ◽  
B.G. Yacobi ◽  
A. Mason
Keyword(s):  
High Efficiency ◽  
Lattice Mismatch ◽  
Low Cost ◽  
Growth Conditions ◽  
Nonradiative Recombination ◽  
Device Structure ◽  
Si Substrates ◽  
Transmission Electron ◽  
Dislocation Densities ◽  
Dislocation Type

There is increasing interest in growing epitaxial GaAs on Si substrates. Such a device structure would allow low-cost substrates to be used for high-efficiency cascade- junction solar cells. However, high-defect densities may result from the large lattice mismatch (∼4%) between the GaAs epilayer and the silicon substrate. These defects can act as nonradiative recombination centers that can degrade the optical and electrical properties of the epitaxially grown GaAs. For this reason, it is important to optimize epilayer growth conditions in order to minimize resulting dislocation densities. The purpose of this paper is to provide an indication of the quality of the epitaxially grown GaAs layers by using transmission electron microscopy (TEM) to examine dislocation type and density as a function of various growth conditions. In this study an intermediate Ge layer was used to avoid nucleation difficulties observed for GaAs growth directly on Si substrates. GaAs/Ge epilayers were grown by molecular beam epitaxy (MBE) on Si substrates in a manner similar to that described previously.

Measurement of lattice parameter at the nanometer scale using convergent-beam microdiffraction from a thermal emission source

1993 ◽  
Vol 51 ◽  
pp. 690-691
Author(s):  
W. T. Pike
Keyword(s):  
Electron Microscope ◽  
Transmission Electron Microscope ◽  
Thermal Emission ◽  
Lattice Parameter ◽  
Scanning Transmission Electron Microscope ◽  
Emission Source ◽  
Device Structure ◽  
Transmission Electron ◽  
Scanning Transmission ◽  
Convergent Beam

With the advent of crystal growth techniques which enable device structure control at the atomic level has arrived a need to determine the crystal structure at a commensurate scale. In particular, in epitaxial lattice mismatched multilayers, it is of prime importance to know the lattice parameter, and hence strain, in individual layers in order to explain the novel electronic behavior of such structures. In this work higher order Laue zone (holz) lines in the convergent beam microdiffraction patterns from a thermal emission transmission electron microscope (TEM) have been used to measure lattice parameters to an accuracy of a few parts in a thousand from nanometer areas of material.Although the use of CBM to measure strain using a dedicated field emission scanning transmission electron microscope has already been demonstrated, the recording of the diffraction pattern at the required resolution involves specialized instrumentation. In this work, a Topcon 002B TEM with a thermal emission source with condenser-objective (CO) electron optics is used.

Trends Related to Power Device Technologies (II)

2010 ◽  
Vol 130 (1) ◽  
pp. 32-36 ◽  
Author(s):  
Ikunorii TAKATA ◽  
Gourab Majumdar
Keyword(s):  
Power Device

Trends Related to Power Device Technologies (I)

2009 ◽  
Vol 129 (12) ◽  
pp. 817-820 ◽  
Author(s):  
Ikunori TAKATA ◽  
Gourab Majumdar
Keyword(s):  
Power Device

Automated Diagonal Slice and View Solution for 3D Device Structure Analysis

2018 ◽  
Author(s):  
Sang Hoon Lee ◽  
Jeff Blackwood ◽  
Stacey Stone ◽  
Michael Schmidt ◽  
Mark Williamson ◽  
...  
Keyword(s):  
Cross Section ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Image Data ◽  
Planar Surface ◽  
Device Structure ◽  
Cross Sectional ◽  
Device Structures ◽  
The Cross ◽  
Planar Analysis

Abstract The cross-sectional and planar analysis of current generation 3D device structures can be analyzed using a single Focused Ion Beam (FIB) mill. This is achieved using a diagonal milling technique that exposes a multilayer planar surface as well as the cross-section. this provides image data allowing for an efficient method to monitor the fabrication process and find device design errors. This process saves tremendous sample-to-data time, decreasing it from days to hours while still providing precise defect and structure data.

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