A new partial SOI power device structure with P-type buried layer

2005 ◽  
Vol 49 (12) ◽  
pp. 1965-1968 ◽  
Author(s):  
Baoxing Duan ◽  
Bo Zhang ◽  
Zhaoji Li
Keyword(s):  
Power Device ◽  
Device Structure ◽  
Buried Layer ◽  
P Type

scholarly journals An Innovated 80V-100V High-Side Side-Isolated N-LDMOS Device

2018 ◽  
Vol 201 ◽  
pp. 02003
Author(s):  
Shao Ming Yangi ◽  
Gene Sheu ◽  
Ting Yao Chien ◽  
Chieh Chih Wu ◽  
Tzu Chieh Lee ◽  
...  
Keyword(s):  
Lower Energy ◽  
3D Structure ◽  
Doping Profile ◽  
Drift Region ◽  
Charge Balance ◽  
Device Structure ◽  
High Side ◽  
Oxide Ratio ◽  
Buried Layer ◽  
P Type

We used TCAD Synopsys 3D tools and device simulators to propose an innovative device structure of 80V-100V high-side NLDMOS by using the silicon to silicon-di-oxide ratio with side trench. The high-side can also be developed by placing an NBL structure which can deliver a high as over 200V isolation voltage. The 3D structure can clear see the optimized linear p-top and n-drift region have better charge balance with linear doping profile to get the benchmark breakdown voltage (BVdss) of 80V with on-resistance (Ron) as low as 130 mΩ-mm2 and 100V with on-resistance as low as 175 mΩ-mm2.The linear p-type buried layer using high dosage and lower energy to achieve the better SOA and higher isolation voltage. Optimized linear p-top and PBL can improve Ron by 32.5% compare to other 100V high side device which have done from reference.

scholarly journals Large Area Emission in p-Type Polymer-Based Light-Emitting Field-Effect Transistors by Incorporating Charge Injection Interlayers

Materials ◽  
2021 ◽  
Vol 14 (4) ◽  
pp. 901
Author(s):  
Gizem Acar ◽  
Muhammad Javaid Iqbal ◽  
Mujeeb Ullah Chaudhry
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Charge Injection ◽  
Limiting Factors ◽  
Hole Injection ◽  
Large Area ◽  
Device Structure ◽  
Light Emitting ◽  
Emission Area ◽  
P Type

Organic light-emitting field-effect transistors (LEFETs) provide the possibility of simplifying the display pixilation design as they integrate the drive-transistor and the light emission in a single architecture. However, in p-type LEFETs, simultaneously achieving higher external quantum efficiency (EQE) at higher brightness, larger and stable emission area, and high switching speed are the limiting factors for to realise their applications. Herein, we present a p-type polymer heterostructure-based LEFET architecture with electron and hole injection interlayers to improve the charge injection into the light-emitting layer, which leads to better recombination. This device structure provides access to hole mobility of ~2.1 cm2 V−1 s−1 and EQE of 1.6% at a luminance of 2600 cd m−2. Most importantly, we observed a large area emission under the entire drain electrode, which was spatially stable (emission area is not dependent on the gate voltage and current density). These results show an important advancement in polymer-based LEFET technology toward realizing new digital display applications.

Hg1−x−yMnxCdyTe Alloys for 1.3−1.8 μm Photodiode Applications

1986 ◽  
Vol 89 ◽  
Author(s):  
S. H. Shin ◽  
J. G. Pasko ◽  
D. S. Lo ◽  
W. E. Tennant ◽  
J. R. Anderson ◽  
...  
Keyword(s):  
Liquid Phase ◽  
Liquid Phase Epitaxy ◽  
Room Temperature ◽  
Reverse Bias ◽  
Fiber Optic ◽  
Superior Performance ◽  
Device Performance ◽  
Device Structure ◽  
Cdte Substrate ◽  
P Type

AbstractHgMnCdTe/CdTe photodiodes with responsivity cutoffs of up to 1.54 pm have been fabricated by liquid phase epitaxy (LPE). The mesa device structure consists of a boron-implanted mosaic fabricated on a p-type Hg1−x−yMnxCdyTe layer grown on a CdTe substrate. A reverse breakdown voltage (VB) of 50 V and a leakage current density of 1.5 × 10−4 A/cm2 at V = −10 V was measured at room temperature (295K). A 0.75 pF capacitance was also measured under a 5 V reverse bias at room temperature. This device performance based on the quaternary HgMnCdTe shows both theoretical and practical promise of superior performance for wavelengths in the range 1.3 to 1.8 μm for fiber optic applications.

Breakdown Field Model for 3C-SiC Power Device Simulations

2018 ◽  
Vol 924 ◽  
pp. 617-620 ◽  
Author(s):  
Hamid Fardi ◽  
Bart van Zeghbroeck
Keyword(s):  
Field Model ◽  
Schottky Diodes ◽  
Power Device ◽  
Breakdown Field ◽  
Power Devices ◽  
High Quality ◽  
Doping Density ◽  
Number Of Publications ◽  
P Type ◽  
Ionization Rates

Modeling and simulation of 3C-SiC power devices such as MOSFETs and diodes requires a model for the breakdown field that is consistent with the Monte-Carlo-simulated ionization rates of electron and holes and supported by experimental results. The challenge one faces is the limited number of publications reporting such calculations and the limited availability of high-quality ionization breakdown data for 3C-SiC diodes. We therefore performed a series of 2D simulations of both n-type and p-type Schottky diodes and p+-n diodes that confirms the general breakdown field trend with doping density obtained from experiments. We uncovered a difference between n-type and p-type diode breakdown behavior, identified the discrepancy between the calculations and the experimental data, and extracted a simple breakdown field model, useful for further 3C-SiC device design and simulation.

A novel multiple super junction power device structure with low specific on-resistance

2014 ◽  
Vol 35 (10) ◽  
pp. 104006 ◽  
Author(s):  
Hui Zhu ◽  
Haiou Li ◽  
Qi Li ◽  
Yuanhao Huang ◽  
Xiaoning Xu ◽  
...  
Keyword(s):  
Power Device ◽  
Device Structure

scholarly journals Simulation of a new hybrid Si/SiC power device for harsh environment applications

2015 ◽  
Vol 2015 (HiTEN) ◽  
pp. 000190-000194
Author(s):  
P.M. Gammon ◽  
C.W. Chan ◽  
P.A. Mawby
Keyword(s):  
Thin Film ◽  
High Temperature ◽  
Silicon On Insulator ◽  
Power Device ◽  
Harsh Environment ◽  
Silicon Thin Film ◽  
Device Structure ◽  
Solar Inverter ◽  
Thermal Simulations ◽  
Soi Substrates

A new power device structure is proposed, conceived to operate in a high temperature, harsh environment, for example within a motor drive application down hole, as an inverter in the engine bay of an electric car, or as a solar inverter in space. The lateral silicon power device resembles a laterally diffused MOSFET (LDMOS), such as those implemented within silicon on insulator (SOI) substrates. However, unlike SOI, the Si thin film has been transferred directly onto a semi-insulating 6H silicon carbide (6H-SiC) substrate via a wafer bonding process. Thermal simulations of the hybrid Si/SiC substrate have shown that the high thermal conductivity of the SiC will have a junction-to-case temperature approximately 4 times less that an equivalent SOI device, reducing the effects of self-heating. Electrical simulations of a 600 V power device, implemented entirely with the silicon thin film, suggest that it will retain the ability of SOI to minimise leakage at high temperature, but does so with 50% less conduction losses.

Influence of a Deep NBL Structure on ESD/Latch-Up Immunities in the Power Device nLDMOS

2013 ◽  
Vol 732-733 ◽  
pp. 1207-1211
Author(s):  
Shen Li Chen ◽  
Tzung Shian Wu
Keyword(s):  
Power Electronics ◽  
High Voltage ◽  
Power Device ◽  
Esd Protection ◽  
Buried Layer ◽  
Latch Up

In this paper, we propose a novel high-voltage (HV) nLDMOS transistor with a small Ron resistance, low trigger voltage (Vt1) and high holding voltage (Vh) characteristics. Here, we introduce a deep N+-buried-layer (NBL) into this HV nLDMOS to evaluate the ESD/latch-up (LU) parameters variation. These electric snapback parameters affect the reliability of proposed device and its performance. Eventually, we expect this proposed HV stucture processed better characteristic behaviors, which can be applied to the power electronics and ESD protection application of HV ICs.

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