Low power modular redundancy: a power efficient fault tolerant approach for digital circuits

2016 ◽  
Vol 35 (3) ◽  
Author(s):  
M. Saeed Ansari ◽  
Ali Mahani ◽  
Karim Mohammadi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Design Methodology ◽  
Digital Circuits ◽  
Fault Tolerant ◽  
Sleep Mode ◽  
Clock Generator ◽  
The Third ◽  
Triple Modular Redundancy ◽  
Modular Redundancy

Purpose To increase protection level against transient faults, circuit designers usually take advantage of redundant structures like Triple Modular Redundancy (TMR). Since redundancy compel a significant power overhead, proposing a low power fault tolerant technique in digital circuits is the main objective of this research work. Design/methodology/approach In order to moderate power consumption, we use a dual to triple modular redundancy. In fact, we put one of the modules in a TMR system in sleep mode while the other two operating modules are producing the same outputs. Once a mismatch is detected, the third one exits the sleep mode and the dual modular redundancy (DMR) approach turns into a conventional TMR. Also a novel stoppable clock generator is proposed to handle the sleep mode of the third module. Finally, a new three-input majority voter, compatible with our proposed technique, is presented. Findings Power analysis of combinational circuit benchmarks, ISCAS85, and ISCAS89 as sequential circuit benchmarks are depicted. Simulation results show the power reduction of up to 30% in comparison with the conventional modular redundancy approach. Originality/value Since modular redundancy is the most effective and the most well-known fault tolerant approach which is widely used in reliable circuits designs, it is important to reduce its power consumption. In this paper configuring the sleep mode operation of a circuit and stoppable clock generator lead to a new TMR technique in which the power consumption is strongly reduced.

scholarly journals A Novel Scheme for Fault Tolerant Computing

2021 ◽  
Vol 3 (1) ◽  
pp. 17-23
Author(s):  
Pramode Ranjan Bhattacharjee ◽  
Keyword(s):  
Fault Tolerant ◽  
Present Scheme ◽  
Triple Modular Redundancy ◽  
Test Input ◽  
Digital Network ◽  
Additional Control ◽  
Majority Voter ◽  
Modular Redundancy ◽  
Primary Output

A novel scheme for ensuring reliability in the operation of a combinational digital network has been offered in this paper. This has been achieved by making use of three copies of the same digital network along with two additional sub-networks, one of which consists of three additional control inputs, which can also be used as additional observable outputs. If both the said two sub-networks are fault free, then the primary output of the network in the present scheme will always give fault-free responses even if a fault (single or multiple) occurs in one of the three copies of the digital network under consideration. Unlike the Triple Modular Redundancy (TMR) scheme, the present scheme does not require any majority voter circuit. Furthermore, unlike the TMR scheme, the additional sub-networks in the present scheme can be tested off-line by predefined test input patterns.

scholarly journals 2.4 GHZ HETERODYNE RECEIVER FOR HEALTHCARE APPLICATION

2016 ◽  
Vol 8 (2) ◽  
pp. 22 ◽  
Author(s):  
Wei Cai ◽  
Frank Shi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Tuning Range ◽  
Low Noise ◽  
Heterodyne Receiver ◽  
The Third ◽  
Noise Amplifier ◽  
Lc Tank ◽  
Down Conversion

<p class="lead">The objective of this research was to design a basic 2.4 GHz heterodyne receiver for healthcare on a 130um CMOS process. The ultimate goal for the wireless industry is to minimize the trade-offs between performance and cost, and between performance and low power consumption design. In the first part, a low noise amplifier (LNA), which is commonly used as the first stage of a receiver, is introduced and simulated. LNA performance greatly affects the overall receiver performance. The LNA was designed at the 2.4 GHz ISM band, using the cascode with an inductive degeneration topology. The second part of this thesis presents a low power 2.4 GHz down conversion Gilbert Cell mixer. In the third part, a high-performance LC-tank CMOS VCO was designed at 2.4 GHz. The design uses using PMOS cross-coupled topology with the varactor for wider tuning range topology. In the first part, a low noise amplifier (LNA) design reaches the NF of 2 dB, has a power consumption of 2.2 mW, and has a gain of 20dB. The second part of this proposal presents a low power 2.4 GHz down conversion Gilbert Cell mixer. The obtained result shows a conversion gain of 14.6 dB and power consumption of 8.2 mW at a 1.3V supply voltage. In the third part, a high-performance LC-tank CMOS VCO was designed at 2.4 GHz. The final simulation of the phase noise is-128 dBc/Hz, and the tuning range is 2.3 GHz-2.5 GHz while the total power consumption is 3.25 mW.<strong> </strong>The performance of the receiver meets the specification requirements of the desired standard.</p>

Cross-Layer Dual Modular Redundancy Hardened Scheme of Flip-Flop Design Based on Sense-Amplifier

2020 ◽  
pp. 2120003
Author(s):  
Zhengfeng Huang ◽  
Zian Su ◽  
Tianming Ni ◽  
Qi Xu ◽  
Haochen Qi ◽  
...  
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Fault Tolerant ◽  
Cross Layer ◽  
Charge Sharing ◽  
Single Node ◽  
Flip Flop ◽  
Sense Amplifier ◽  
Modular Redundancy ◽  
Voltage Swing

As the demand for low-power and high-speed logic circuits increases, the design of differential flip-flops based on sense-amplifier (SAFF), which have excellent power and speed characteristics, has become more and more popular. Conventional SAFF (Con SAFF) and improved SAFF designs focus more on the improvement of speed and power consumption, but ignore their Single-Event-Upset (SEU) sensitivity. In fact, SAFF is more susceptible to particle impacts due to the small voltage swing required for differential input in the master stage. Based on the SEU vulnerability of SAFF, this paper proposes a novel scheme, namely cross-layer Dual Modular Redundancy (DMR), to improve the robustness of SAFF. That is, unit-level DMR technology is performed in the master stage, while transistor-level stacking technology is used in the slave stage. This scheme can be applied to some current typical SAFF designs, such as Con SAFF, Strollo SAFF, Ahmadi SAFF, Jeong SAFF, etc. Detailed HSPICE simulation results demonstrate that hardened SAFF designs can not only fully tolerate the Single Node Upset of sensitive nodes, but also partially tolerate the Double Node Upset caused by charge sharing. Besides, compared with the conventional DMR hardened scheme, the proposed cross-layer DMR hardened scheme not only has the same fault-tolerant characteristics, but also greatly reduces the delay, area and power consumption.

scholarly journals A Fault Tolerant Voter for Approximate Triple Modular Redundancy

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 332 ◽  
Author(s):  
Tooba Arifeen ◽  
Abdus Hassan ◽  
Jeong-A Lee
Keyword(s):  
Fault Tolerant ◽  
Triple Modular Redundancy ◽  
Area Overhead ◽  
Final Output ◽  
Working Principle ◽  
Fault Masking ◽  
Internal Faults ◽  
Modular Redundancy ◽  
Power Delay Product

Approximate Triple Modular Redundancy has been proposed in the literature to overcome the area overhead issue of Triple Modular Redundancy (TMR). The outcome of TMR/Approximate TMR modules serves as the voter input to produce the final output of a system. Because the working principle of Approximate TMR conditionally allows one of the approximate modules to differ from the original circuit, it is critical for Approximate TMR that a voter not only be tolerant toward its internal faults but also toward faults that occur at the voter inputs. Herein, we present a novel compact voter for Approximate TMR using pass transistors and quadded transistor level redundancy to achieve a higher fault masking. The design also targets a better Quality of Circuit (QoC), a new metric which we have proposed for highlighting the ability of a circuit to fully mask all possible internal faults for an input vector. Comparing the fault masking features with those of existing works, the proposed voter delivered upto 45.1%, 62.5%, 26.6% improvement in Fault Masking Ratio (FMR), QoC, and reliability, respectively. With respect to the electrical characteristics, our proposed voter can achieve an improvement of up to 50% and 56% in terms of the transistor count and power delay product, respectively.

scholarly journals Various Nano-Scale Technologies: Lower Hardware Complexity of Alu Realizing Utilizing FS-GDI Approach IN 45nm AND 130nm

2021 ◽  
Vol 14 (1) ◽  
pp. 9-34
Author(s):  
Mohsen A. M. El-Bendary ◽  
◽  
M. Ayman ◽  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Delay Time ◽  
Digital Circuits ◽  
Logic Gates ◽  
Propagation Delay ◽  
Hardware Complexity ◽  
Simulation Experiments ◽  
Lower Power ◽  
Full Swing

Full Swing Gate Diffusion Input (FS-GDI) approach is power effective approach for realizing the different logic gates. In this research, this approach is utilized for realizing different four ALU design using 45nm and 130nm technologies. Also, the different low power VLSI logic styles and related past works are discussed with considering the 45nm and 65nm technologies for implementing various circuits for studying the technology size impact. The performance of the proposed ALU design is evaluated through power consumption, propagation delay and number of transistors. The variation of the ALU performance due to the used 45nm and 130nm technologies has been studied. The simulation is carried out utilizing Cadence Virtuoso simulator. The simulation experiments revealed the energy of the 4-bit ALU reduced by 32% compared to CMOS-based design and area of the digital circuits reducing. Regarding the different nano technologies, 45nm technology provides lower power consumption and delay time deceasing compared to ALU unit by 130nm technology. The presented approach of low hardware complexity achieves simplicity of the required ALU hardware through reducing the number of transistors.

scholarly journals Hybrid fault tolerant control for air–fuel ratio control of internal combustion gasoline engine using Kalman filters with advanced redundancy

2019 ◽  
Vol 52 (5-6) ◽  
pp. 473-492 ◽  
Author(s):  
Arslan Ahmed Amin ◽  
Khalid Mahmood-ul-Hasan
Keyword(s):  
Control System ◽  
Kalman Filters ◽  
Active Fault ◽  
Fault Tolerant ◽  
Fault Tolerant Control ◽  
Internal Combustion ◽  
Sensors And Actuators ◽  
Triple Modular Redundancy ◽  
Fuel Ratio ◽  
Modular Redundancy

In this paper, a hybrid fault tolerant control system is proposed for air–fuel ratio control of internal combustion gasoline engines based on Kalman filters and triple modular redundancy. Hybrid fault tolerant control system possesses properties of both active fault tolerant control system and passive fault tolerant control system. As part of active fault tolerant control system, fault detection and isolation unit is designed using Kalman filters to provide estimated values of the sensors to the engine controller in case of faults in the sensors. As part of passive fault tolerant control system, a dedicated proportional–integral feedback controller is incorporated to maintain air–fuel ratio by adjusting the throttle actuator in the fuel supply line in faulty and noisy conditions for robustness to faults and sensors’ noise. Redundancy is proposed in the sensors and actuators as a simultaneous failure of more than one sensor, and failure of the single actuator will cause the engine shutdown. Advanced redundancy protocol triple modular redundancy is proposed for the sensors and dual redundancy is proposed for actuators. Simulation results in the MATLAB Simulink environment show that the proposed system remains stable during faults in the sensors and actuators. It also maintains air–fuel ratio without any degradation in the faulty conditions and is robust to noise. Finally, the probabilistic reliability analysis of the proposed model is carried out. The study shows that the proposed hybrid fault tolerant control system with redundant components presents a novel and highly reliable solution for the air–fuel ratio control in internal combustion engines to prevent engine shutdown and production loss for greater profits.

A New-High Speed-Low Power-Carry Select Adder Using Modified GDI Technique

2015 ◽  
Vol 4 (3) ◽  
pp. 173
Author(s):  
M. Anitha ◽  
J.Princy Joice ◽  
Rexlin Sheeba.I
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Digital Circuits ◽  
Lower Cost ◽  
Block Structure ◽  
Propagation Delay ◽  
Digital Systems ◽  
Novel Technique ◽  
Degradation Problem

Adders are of fundamental importance in a wide variety of digital systems. This paper presents a novel bit block structure which computes propagate signals as carry strength. Power consumption is one of the most significant parameters of carry select adder.The proposed method aims on GDI(Gate Diffusion Input) Technique. Modified GDI is a novel technique for low power digital circuits design further to reduce the swing degradation problem. This techniques allows reduction in power consumption, carry propagation delay and transistor count of the carry select adder.This technique can be used to reduce the number of transistors compared to conventional CSLA and made comparison with known conventional adders which gives that the usage of carry-strength signals allows high-speed adders to be realised at lower cost as well as consuming lower power than previous designs. Hence, this paper we are concentrating on the area level &amp;we are reducing the power using modified GDI logic.

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