scholarly journals Various Nano-Scale Technologies: Lower Hardware Complexity of Alu Realizing Utilizing FS-GDI Approach IN 45nm AND 130nm

2021 ◽  
Vol 14 (1) ◽  
pp. 9-34
Author(s):  
Mohsen A. M. El-Bendary ◽  
◽  
M. Ayman ◽  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Delay Time ◽  
Digital Circuits ◽  
Logic Gates ◽  
Propagation Delay ◽  
Hardware Complexity ◽  
Simulation Experiments ◽  
Lower Power ◽  
Full Swing

Full Swing Gate Diffusion Input (FS-GDI) approach is power effective approach for realizing the different logic gates. In this research, this approach is utilized for realizing different four ALU design using 45nm and 130nm technologies. Also, the different low power VLSI logic styles and related past works are discussed with considering the 45nm and 65nm technologies for implementing various circuits for studying the technology size impact. The performance of the proposed ALU design is evaluated through power consumption, propagation delay and number of transistors. The variation of the ALU performance due to the used 45nm and 130nm technologies has been studied. The simulation is carried out utilizing Cadence Virtuoso simulator. The simulation experiments revealed the energy of the 4-bit ALU reduced by 32% compared to CMOS-based design and area of the digital circuits reducing. Regarding the different nano technologies, 45nm technology provides lower power consumption and delay time deceasing compared to ALU unit by 130nm technology. The presented approach of low hardware complexity achieves simplicity of the required ALU hardware through reducing the number of transistors.

A New-High Speed-Low Power-Carry Select Adder Using Modified GDI Technique

2015 ◽  
Vol 4 (3) ◽  
pp. 173
Author(s):  
M. Anitha ◽  
J.Princy Joice ◽  
Rexlin Sheeba.I
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Digital Circuits ◽  
Lower Cost ◽  
Block Structure ◽  
Propagation Delay ◽  
Digital Systems ◽  
Novel Technique ◽  
Degradation Problem

Adders are of fundamental importance in a wide variety of digital systems. This paper presents a novel bit block structure which computes propagate signals as carry strength. Power consumption is one of the most significant parameters of carry select adder.The proposed method aims on GDI(Gate Diffusion Input) Technique. Modified GDI is a novel technique for low power digital circuits design further to reduce the swing degradation problem. This techniques allows reduction in power consumption, carry propagation delay and transistor count of the carry select adder.This technique can be used to reduce the number of transistors compared to conventional CSLA and made comparison with known conventional adders which gives that the usage of carry-strength signals allows high-speed adders to be realised at lower cost as well as consuming lower power than previous designs. Hence, this paper we are concentrating on the area level &we are reducing the power using modified GDI logic.

scholarly journals A New Systematic Encoding  Circuit of Hamming (15, 11) Using Low-Power XOR-FS-GDI Based Logic Gate: Fast Computing and Efficient Area FEC

2021 ◽  
Author(s):  
Mohsen El-Bendary ◽  
O El-Badry
Keyword(s):  
Low Power ◽  
Delay Time ◽  
Power Efficiency ◽  
Logic Gate ◽  
Logic Gates ◽  
The Other ◽  
Simulation Experiments ◽  
Hamming Codes ◽  
Communications Systems ◽  
Other Hand

Abstract Due to the power efficiency importance of digital signal processing and data protection in different communications systems, this paper proposes an efficient design of different Hamming Codes utilizing Full Swing- Gate Diffusion Input (FS-GDI) approach. The proposed codes design aims to improve the power efficiency and the required area through reducing the required number of transistors. FS-GDI is a new low power VLSI design approach, it is a power effective approach for realizing the different logic gates. In this work, the Hamming codes (11, 7) and (15, 11) are designed by utilizing the original GDI, FS-GDI and the traditional CMOS approaches. The amount of consumed power, delay time, Power Delay Product (PDP) and hardware simplicity-Number of Transistors (No. Ts) are employed as a metrics for evaluating the efficiency of the proposed design compared to the traditional design. The design simulation experiments are executed utilizing Cadence Virtuoso simulator package under 65nm technology. The simulation experiments revealed these proposed codes achieve delay time reduction by 52.91% and 10% for Hamming codes (7, 4) and (11, 7), respectively On the other hand, the Hardware (H/W) of these codes became more simple where the H/W simplicity of the used Hamming codes is reduced 50 % CMOS approaches respectively. From the results analysis, the proposed design achieves efficient power and the delay optimizing of Hamming codes utilizing the FS-GDI approach. On the other hand, the power consumption and area in communications systems due to the encoding process can be reduces.

scholarly journals Design and Analysis of Gate All Around Tunnel FET based Ring Oscillator Circuit

2019 ◽  
Vol 8 (2) ◽  
pp. 2415-2420
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Propagation Delay ◽  
Active Power ◽  
Vlsi Circuits ◽  
Ring Oscillator ◽  
Oscillator Circuit ◽  
Lower Power ◽  
Tunnel Fet ◽  
Simulation Results

In this work, we have designed and simulated a Gate All Around TFET (GAATFET) based 3 stage ring oscillator circuit and compared its performance with the CMOS based counterpart. The results of SPICE simulations indicate that GAATFET based ring oscillator circuit consumes 3.5 times lower power consumption in active mode than CMOS based ring oscillator. However, 0.43 ns and 0.17 ns of propagation delay is observed for GAATFET based ring oscillator and CMOS based ring oscillator circuit respectively. The obtained output waveform frequency for CMOS based ring oscillator is 2.5 times higher than the GAAATFET based ring oscillator. Further, undershoot is also investigated and it is found that the amplitude of undershoot in case of GAATFET based oscillator is roughly 6.5 times more as compared to CMOS based counterpart. The undershoot and delay observed in case of GAATFET based ring oscillator can be over-shaded by the fact that it has lower active power consumption than the CMOS based ring oscillator. Simulation results signify that GAATFET based ring oscillator can be deployed in future low power VLSI circuits and systems.

scholarly journals HIGH SPEED ADDER USING GDI TECHNIQUE

2020 ◽  
Vol 5 (2) ◽  
pp. 130-136
Author(s):  
Merrin Mary Solomon ◽  
Neeraj Gupta ◽  
Rashmi Gupta
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Digital Circuits ◽  
Full Adder ◽  
Low Complexity ◽  
Propagation Delay ◽  
Logic Design ◽  
Reduce Power Consumption

Full adder is an important component for designing a processor. As the complexity of the circuit increases, the speed of operation becomes a major concern. Nowadays there are various architectures that exist for full adders. In this paper we will discuss about designing a low power and high speed full adder using Gate Diffusion Input technique. GDI is one of the present day methods through which one can design logical circuits. This technique will reduce power consumption, propagation delay, and area of digital circuits as well as maintain low complexity of logic design. The performance of the proposed design is compared with the contemporary full adder designs.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

A Low-Power and Area-Efficient 64-Bit Digital Comparator

2016 ◽  
Vol 25 (12) ◽  
pp. 1650148 ◽  
Author(s):  
N. V. Vijaya Krishna Boppana ◽  
Saiyu Ren
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Resource Sharing ◽  
Portable Devices ◽  
Worst Case ◽  
Lower Power ◽  
Digital Comparator ◽  
Area Efficient

A new low-power and area-efficient radix-4 tree-based 64-bit digital comparator is presented in this paper. The proposed design with 64 XOR-XNOR (XE) blocks is custom implemented in 90[Formula: see text]nm 1.2[Formula: see text]V multi-threshold technology using Cadence-Virtuoso layout editor. The 64 bit comparator has an area of 1009[Formula: see text][Formula: see text], a worst case delay of 858[Formula: see text]ps, and a power consumption of 898[Formula: see text]uW at 1[Formula: see text]G bit/s. The two features, lower power consumption and smaller area compared to other published comparators, make the proposed design most suitable for low-power portable devices. Resource sharing is an important feature for the proposed design. The 64 XE blocks occupy approximately 60% (600[Formula: see text][Formula: see text]) of the total comparator area and contributes 54% (484[Formula: see text][Formula: see text]W) of the total worst power consumption. The 64 XE blocks can also be used to design XE based 64-bit adders, encryption devices, etc.

A NEW ROBUST AND HIGH-PERFORMANCE HYBRID FULL ADDER CELL

2011 ◽  
Vol 20 (04) ◽  
pp. 641-655 ◽  
Author(s):  
REZA FAGHIH MIRZAEE ◽  
MOHAMMAD HOSSEIN MOAIYERI ◽  
HAMID KHORSAND ◽  
KEIVAN NAVI
Keyword(s):  
Power Consumption ◽  
Great Improvement ◽  
High Performance ◽  
Full Adder ◽  
Good Choice ◽  
Lower Power ◽  
Pvt Variations ◽  
Power Delay Product ◽  
Full Swing ◽  
Hspice Simulation

A new 1-bit hybrid Full Adder cell is presented in this paper with the aim of reaching a robust and high-performance adder structure. While most of recent Full Adders are proposed with the purpose of using fewer transistors, they suffer from some disadvantages such as output or internal non-full-swing nodes and poor driving capability. Considering these drawbacks, they might not be a good choice to operate in a practical environment. Lowering the number of transistors can inherently lead to smaller occupied area, higher speed and lower power consumption. However, other parameters, such as robustness to PVT variations and rail-to-rail operation, should also be considered. While the robustness is taken into account, HSPICE simulation demonstrates a great improvement in terms of speed and power-delay product (PDP).

Low power modular redundancy: a power efficient fault tolerant approach for digital circuits

2016 ◽  
Vol 35 (3) ◽  
Author(s):  
M. Saeed Ansari ◽  
Ali Mahani ◽  
Karim Mohammadi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Design Methodology ◽  
Digital Circuits ◽  
Fault Tolerant ◽  
Sleep Mode ◽  
Clock Generator ◽  
The Third ◽  
Triple Modular Redundancy ◽  
Modular Redundancy

Purpose To increase protection level against transient faults, circuit designers usually take advantage of redundant structures like Triple Modular Redundancy (TMR). Since redundancy compel a significant power overhead, proposing a low power fault tolerant technique in digital circuits is the main objective of this research work. Design/methodology/approach In order to moderate power consumption, we use a dual to triple modular redundancy. In fact, we put one of the modules in a TMR system in sleep mode while the other two operating modules are producing the same outputs. Once a mismatch is detected, the third one exits the sleep mode and the dual modular redundancy (DMR) approach turns into a conventional TMR. Also a novel stoppable clock generator is proposed to handle the sleep mode of the third module. Finally, a new three-input majority voter, compatible with our proposed technique, is presented. Findings Power analysis of combinational circuit benchmarks, ISCAS85, and ISCAS89 as sequential circuit benchmarks are depicted. Simulation results show the power reduction of up to 30% in comparison with the conventional modular redundancy approach. Originality/value Since modular redundancy is the most effective and the most well-known fault tolerant approach which is widely used in reliable circuits designs, it is important to reduce its power consumption. In this paper configuring the sleep mode operation of a circuit and stoppable clock generator lead to a new TMR technique in which the power consumption is strongly reduced.

Design of ultra compact all-optical XOR and AND logic gates with low power consumption

2011 ◽  
Vol 284 (14) ◽  
pp. 3528-3533 ◽  
Author(s):  
Yuhei Ishizaka ◽  
Yuki Kawaguchi ◽  
Kunimasa Saitoh ◽  
Masanori Koshiba
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Logic Gates ◽  
Low Power Consumption ◽  
All Optical
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