Short-channel effect in fully depleted SOI MOSFETs

1989 ◽  
Vol 36 (2) ◽  
pp. 399-402 ◽  
Author(s):  
K.K. Young
Keyword(s):  
Short Channel ◽  
Short Channel Effect ◽  
Fully Depleted ◽  
Channel Effect

scholarly journals Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits

2019 ◽  
Vol 2019 ◽  
pp. 1-9
Author(s):  
Zhaopeng Wei ◽  
Gilles Jacquemod ◽  
Yves Leduc ◽  
Emeric de Foucauld ◽  
Jerome Prouvee ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Analog Circuits ◽  
Silicon On Insulator ◽  
Ring Oscillator ◽  
Passive Component ◽  
Short Channel ◽  
Short Channel Effect ◽  
Back Gate ◽  
Fully Depleted ◽  
Channel Effect

Analog integrated circuits never follow the Moore’s Law. This is particularly right for passive component. Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology using some advantages of the FDSOI (Fully Depleted Silicon on Insulator) technology in order to reduce the size of analog cells. First, a current mirror was chosen to illustrate and validate a new design. Measured currents, with 35nm transistor length, have validated our new cross-coupled back-gate topology. Then, a VCRO (Voltage Controlled Ring Oscillator) based on complementary inverter is also used to remove passive components reducing the size of the circuit.

Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology

2012 ◽  
Author(s):  
Yuk L. Tsang ◽  
Xiang D. Wang ◽  
Reyhan Ricklefs ◽  
Jason Goertz
Keyword(s):  
Threshold Voltage ◽  
Electrical Characterization ◽  
Cmos Technology ◽  
Short Channel ◽  
Visual Defect ◽  
Subthreshold Region ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Transistor Model

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.

Improved Short Channel Effect Control in Bulk FinFETs With Vertical Implantation to Form Self-Aligned Halo and Punch-Through Stop Pocket

2015 ◽  
Vol 36 (7) ◽  
pp. 648-650 ◽  
Author(s):  
Miao Xu ◽  
Huilong Zhu ◽  
Lichuan Zhao ◽  
Huaxiang Yin ◽  
Jian Zhong ◽  
...  
Keyword(s):  
Short Channel ◽  
Short Channel Effect ◽  
Channel Effect

Suppression of short channel effect in organic thin film transistors

2007 ◽  
Vol 91 (11) ◽  
pp. 113508 ◽  
Author(s):  
K. Tukagoshi ◽  
F. Fujimori ◽  
T. Minari ◽  
T. Miyadera ◽  
T. Hamano ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Organic Thin Film Transistors ◽  
Organic Thin Film ◽  
Short Channel ◽  
Short Channel Effect ◽  
Channel Effect

Short-channel Effect in 4H-SiC Ion-implanted Planar MESFETs

2011 ◽  
Vol 59 (3) ◽  
pp. 2368-2371 ◽  
Author(s):  
Jeonghyuk Yim ◽  
Han Seok Seo ◽  
Do Hyun Lee ◽  
Chang Hyun Kim ◽  
Hyeong Joon Kim
Keyword(s):  
Short Channel ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Ion Implanted
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