scholarly journals Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits

2019 ◽  
Vol 2019 ◽  
pp. 1-9
Author(s):  
Zhaopeng Wei ◽  
Gilles Jacquemod ◽  
Yves Leduc ◽  
Emeric de Foucauld ◽  
Jerome Prouvee ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Analog Circuits ◽  
Silicon On Insulator ◽  
Ring Oscillator ◽  
Passive Component ◽  
Short Channel ◽  
Short Channel Effect ◽  
Back Gate ◽  
Fully Depleted ◽  
Channel Effect

Analog integrated circuits never follow the Moore’s Law. This is particularly right for passive component. Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology using some advantages of the FDSOI (Fully Depleted Silicon on Insulator) technology in order to reduce the size of analog cells. First, a current mirror was chosen to illustrate and validate a new design. Measured currents, with 35nm transistor length, have validated our new cross-coupled back-gate topology. Then, a VCRO (Voltage Controlled Ring Oscillator) based on complementary inverter is also used to remove passive components reducing the size of the circuit.

Suppression of Short-Channel Effects in 4H-SiC Trench MOSFETs

2019 ◽  
Vol 963 ◽  
pp. 613-616
Author(s):  
Tomoyasu Ishii ◽  
Shinichiro Kuroki ◽  
Hiroshi Sezaki ◽  
Seiji Ishikawa ◽  
Tomonori Maeda ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Threshold Voltage ◽  
High Frequency ◽  
Short Channel Effects ◽  
Short Channel ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Channel Effects ◽  
Trench Structure ◽  
High Frequency Operation

Submicron 4H-SiC MOSFETs are attractive for high frequency operation of 4H-SiC integrated circuits. However, the short channel effects, such as threshold voltage lowering, would be induced at the short-channel devices. In this work, short channel effects were investigated with planar and trench 4H-SiC MOSFETs, and the suppression of the short channel effect with the trench structure was achieved.

Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology

2012 ◽  
Author(s):  
Yuk L. Tsang ◽  
Xiang D. Wang ◽  
Reyhan Ricklefs ◽  
Jason Goertz
Keyword(s):  
Threshold Voltage ◽  
Electrical Characterization ◽  
Cmos Technology ◽  
Short Channel ◽  
Visual Defect ◽  
Subthreshold Region ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Transistor Model

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.

Sign in / Sign up

Export Citation Format

Share Document