Modeling on the Channel-To-S/D Capacitance and the Short Channel Effect for 0.1μm Fully Depleted SOI-MOSFET

This paper describes the characteristics comparison of bulk FINFET and SOI FINFET. The scaling trend in device dimension require limit on short channel effect through the control of subthreshold slope and DIBL characteristics.It can be achieved by proper device design. The subthreshold characteristics are plotted with the variation of gate voltage for different doping profile .This paper also compares the performance improvement of Multi-gate Bulk and SOI MOSFET over Single-gate bulk and SOI MOSFET.The simulation results are obtained with the help of TCAD 3-D device simulator are well matched with the ideal characteristics.

Download Full-text

Deep submicrometer double-gate fully-depleted SOI PMOS devices: a concise short-channel effect threshold voltage model using a quasi-2D approach

IEEE Transactions on Electron Devices ◽

10.1109/16.535323 ◽

1996 ◽

Vol 43 (9) ◽

pp. 1387-1393 ◽

Cited By ~ 34

Author(s):

Shiao-Shien Chen ◽

J.B. Kuo

Keyword(s):

Threshold Voltage ◽

Double Gate ◽

Short Channel ◽

Short Channel Effect ◽

Fully Depleted ◽

Channel Effect ◽

Deep Submicrometer ◽

Threshold Voltage Model

Download Full-text

Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits

Active and Passive Electronic Components ◽

10.1155/2019/4578501 ◽

2019 ◽

Vol 2019 ◽

pp. 1-9

Author(s):

Zhaopeng Wei ◽

Gilles Jacquemod ◽

Yves Leduc ◽

Emeric de Foucauld ◽

Jerome Prouvee ◽

...

Keyword(s):

Integrated Circuits ◽

Analog Circuits ◽

Silicon On Insulator ◽

Ring Oscillator ◽

Passive Component ◽

Short Channel ◽

Short Channel Effect ◽

Back Gate ◽

Fully Depleted ◽

Channel Effect

Analog integrated circuits never follow the Moore’s Law. This is particularly right for passive component. Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology using some advantages of the FDSOI (Fully Depleted Silicon on Insulator) technology in order to reduce the size of analog cells. First, a current mirror was chosen to illustrate and validate a new design. Measured currents, with 35nm transistor length, have validated our new cross-coupled back-gate topology. Then, a VCRO (Voltage Controlled Ring Oscillator) based on complementary inverter is also used to remove passive components reducing the size of the circuit.

Download Full-text

Short-channel effect in fully depleted SOI MOSFETs

IEEE Transactions on Electron Devices ◽

10.1109/16.19942 ◽

1989 ◽

Vol 36 (2) ◽

pp. 399-402 ◽

Cited By ~ 572

Author(s):

K.K. Young

Keyword(s):

Short Channel ◽

Short Channel Effect ◽

Fully Depleted ◽

Channel Effect

Download Full-text

Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology

ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2012p0106 ◽

2012 ◽

Author(s):

Yuk L. Tsang ◽

Xiang D. Wang ◽

Reyhan Ricklefs ◽

Jason Goertz

Keyword(s):

Threshold Voltage ◽

Electrical Characterization ◽

Cmos Technology ◽

Short Channel ◽

Visual Defect ◽

Subthreshold Region ◽

Short Channel Effect ◽

Channel Effect ◽

Transistor Model

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.

Download Full-text