Full software analysis and impedance matching of radio frequency CMOS integrated circuits

Abstract Highly-integrated radio frequency and mixed-mode devices that are manufactured in deep-submicron or more advanced CMOS processes are becoming more complex to analyze. The increased complexity presents us with many eccentric failure mechanisms that are uniquely different from traditional failure mechanisms found during failure analysis on digital logic applications. This paper presents a novel methodology to overcome the difficulties and discusses two case studies which demonstrate the application of the methodology. Through the case studies, the methodology was proven to be a successful approach. It is also proved how this methodology would work for such non-recognizable failures.

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A Study on the Effect of the Structural Parameters and Internal Mechanism of a Bilateral Gate-Controlled S/D Symmetric and Interchangeable Bidirectional Tunnel Field Effect Transistor

Nanoscale Research Letters ◽

10.1186/s11671-021-03561-8 ◽

2021 ◽

Vol 16 (1) ◽

Author(s):

Xiaoshi Jin ◽

Yicheng Wang ◽

Kailu Ma ◽

Meile Wu ◽

Xi Liu ◽

...

Keyword(s):

Integrated Circuits ◽

Field Effect ◽

Field Effect Transistor ◽

Structural Parameters ◽

Cmos Integrated Circuits ◽

Region Length ◽

Internal Mechanism ◽

Effect Transistor ◽

Tunnel Field Effect Transistor ◽

Switching Characteristics

AbstractA bilateral gate-controlled S/D symmetric and interchangeable bidirectional tunnel field effect transistor (B-TFET) is proposed in this paper, which shows the advantage of bidirectional switching characteristics and compatibility with CMOS integrated circuits compared to the conventional asymmetrical TFET. The effects of the structural parameters, e.g., the doping concentrations of the N+ region and P+ region, length of the N+ region and length of the intrinsic region, on the device performances, e.g., the transfer characteristics, Ion–Ioff ratio and subthreshold swing, and the internal mechanism are discussed and explained in detail.

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Optimization of spaceflight millimeter-wave impedance matching networks using laser trimming

International Journal of Microwave and Wireless Technologies ◽

10.1017/s1759078721000180 ◽

2021 ◽

pp. 1-7

Author(s):

K. Parow-Souchon ◽

D. Cuadrado-Calle ◽

S. Rea ◽

M. Henry ◽

M. Merritt ◽

...

Keyword(s):

Integrated Circuits ◽

Millimeter Wave ◽

Impedance Matching ◽

Wave Impedance ◽

Low Noise ◽

Device Performance ◽

Interface Circuits ◽

Interface Circuit ◽

Noise Amplifier

Abstract Realizing packaged state-of-the-art performance of monolithic microwave integrated circuits (MMICs) operating at millimeter wavelengths presents significant challenges in terms of electrical interface circuitry and physical construction. For instance, even with the aid of modern electromagnetic simulation tools, modeling the interaction between the MMIC and its package embedding circuit can lack the necessary precision to achieve optimum device performance. Physical implementation also introduces inaccuracies and requires iterative interface component substitution that can produce variable results, is invasive and risks damaging the MMIC. This paper describes a novel method for in situ optimization of packaged millimeter-wave devices using a pulsed ultraviolet laser to remove pre-selected areas of interface circuit metallization. The method was successfully demonstrated through the optimization of a 183 GHz low noise amplifier destined for use on the MetOp-SG meteorological satellite series. An improvement in amplifier output return loss from an average of 12.9 dB to 22.7 dB was achieved across an operational frequency range of 175–191 GHz and the improved circuit reproduced. We believe that our in situ tuning technique can be applied more widely to planar millimeter-wave interface circuits that are critical in achieving optimum device performance.

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