Radio Frequency CMOS Integrated Circuits for-Low Power Transceiver Applications

Abstract Highly-integrated radio frequency and mixed-mode devices that are manufactured in deep-submicron or more advanced CMOS processes are becoming more complex to analyze. The increased complexity presents us with many eccentric failure mechanisms that are uniquely different from traditional failure mechanisms found during failure analysis on digital logic applications. This paper presents a novel methodology to overcome the difficulties and discusses two case studies which demonstrate the application of the methodology. Through the case studies, the methodology was proven to be a successful approach. It is also proved how this methodology would work for such non-recognizable failures.

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Design and Verification of Low-Power Integrated Circuits

10.3403/30318829u ◽

2015 ◽

Keyword(s):

Integrated Circuits ◽

Low Power

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SiGe Radio Frequency ICs for Low-Power Portable Communication

Proceedings of the IEEE ◽

10.1109/jproc.2005.852227 ◽

2005 ◽

Vol 93 (9) ◽

pp. 1598-1623 ◽

Cited By ~ 22

Author(s):

J.R. Long

Keyword(s):

Low Power ◽

Radio Frequency ◽

Portable Communication

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The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

Applied Sciences ◽

10.3390/app11010429 ◽

2021 ◽

Vol 11 (1) ◽

pp. 429

Author(s):

Min-Su Kim ◽

Youngoo Yang ◽

Hyungmo Koo ◽

Hansik Oh

Keyword(s):

Integrated Circuits ◽

Embedded System ◽

Low Power ◽

High Speed ◽

Cmos Technology ◽

Clock Frequency ◽

Clock Generation ◽

Allocation Method ◽

Evaluation Board ◽

28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

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A Study on the Effect of the Structural Parameters and Internal Mechanism of a Bilateral Gate-Controlled S/D Symmetric and Interchangeable Bidirectional Tunnel Field Effect Transistor

Nanoscale Research Letters ◽

10.1186/s11671-021-03561-8 ◽

2021 ◽

Vol 16 (1) ◽

Author(s):

Xiaoshi Jin ◽

Yicheng Wang ◽

Kailu Ma ◽

Meile Wu ◽

Xi Liu ◽

...

Keyword(s):

Integrated Circuits ◽

Field Effect ◽

Field Effect Transistor ◽

Structural Parameters ◽

Cmos Integrated Circuits ◽

Region Length ◽

Internal Mechanism ◽

Effect Transistor ◽

Tunnel Field Effect Transistor ◽

Switching Characteristics

AbstractA bilateral gate-controlled S/D symmetric and interchangeable bidirectional tunnel field effect transistor (B-TFET) is proposed in this paper, which shows the advantage of bidirectional switching characteristics and compatibility with CMOS integrated circuits compared to the conventional asymmetrical TFET. The effects of the structural parameters, e.g., the doping concentrations of the N+ region and P+ region, length of the N+ region and length of the intrinsic region, on the device performances, e.g., the transfer characteristics, Ion–Ioff ratio and subthreshold swing, and the internal mechanism are discussed and explained in detail.

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