Bar-coated polymer ambipolar field-effect transistors and complementary integrated circuits for large area electronics

Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding.

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Experimental and molecular dynamics studies of an ultra-fast sequential hydrogen plasma process for fabricating phosphorene-based sensors

Scientific Reports ◽

10.1038/s41598-021-95463-z ◽

2021 ◽

Vol 11 (1) ◽

Author(s):

M. Rajabali ◽

H. Asgharyan ◽

V. Fadaei Naeini ◽

A. Boudaghi ◽

B. Zabihi ◽

...

Keyword(s):

Electron Microscopy ◽

Molecular Dynamics ◽

Field Effect ◽

Field Effect Transistors ◽

Hydrogen Plasma ◽

Device Fabrication ◽

Dynamics Simulation ◽

Red Phosphorus ◽

Large Area ◽

Low Concentration

AbstractLow concentration phosphorene-based sensors have been fabricated using a facile and ultra-fast process which is based on an exfoliation-free sequential hydrogen plasma treatment to convert the amorphous phosphorus thin film into mono- or few-layered phosphorene sheets. These sheets have been realized directly on silicon substrates followed by the fabrication of field-effect transistors showing the low leakage current and reasonable mobility for the nano-sensors. Being capable of covering the whole surface of the silicon substrate, red phosphorus (RP) coated substrate has been employed to achieve large area phosphorene sheets. Unlike the available techniques including mechanical exfoliation, there is no need for any exfoliation and/or transfer step which is significant progress in shortening the device fabrication procedure. These phosphorene sheets have been examined using transmission electron microscopy (TEM), Scanning electron microscopy (SEM), Raman spectroscopy and atomic-force microscopy (AFM). Electrical output in different states of the crystallization as well as its correlation with the test parameters have been also extensively used to examine the evolution of the phosphorene sheets. By utilizing the fabricated devices, the sensitivity of the phosphorene based-field effect transistors to the soluble L-Cysteine in low concentrations has been studied by measuring the FET response to the different concentrations. At a gate voltage of − 2.5 V, the range of 0.07 to 0.60 mg/ml of the L-Cysteine has been distinguishably detected presenting a gate-controlled sensor for a low-concentration solution. A reactive molecular dynamics simulation has been also performed to track the details of this plasma-based crystallization. The obtained results showed that the imparted energy from hydrogen plasma resulted in a phase transition from a system containing red phosphorus atoms to the crystal one. Interestingly and according to the simulation results, there is a directional preference of crystal growth as the crystalline domains are being formed and RP atoms are more likely to re-locate in armchair than in zigzag direction.

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Nanonet: Low-temperature-processed tellurium nanowire network for scalable p-type field-effect transistors and a highly sensitive phototransistor array

NPG Asia Materials ◽

10.1038/s41427-021-00314-y ◽

2021 ◽

Vol 13 (1) ◽

Author(s):

Muhammad Naqi ◽

Kyung Hwan Choi ◽

Hocheon Yoo ◽

Sudong Chae ◽

Bum Jun Kim ◽

...

Keyword(s):

Low Temperature ◽

Field Effect ◽

High Performance ◽

Field Effect Transistors ◽

Optical Measurements ◽

Electrical Performance ◽

Large Area ◽

Nanowire Network ◽

P Type ◽

Nanowire Networks

AbstractLow-temperature-processed semiconductors are an emerging need for next-generation scalable electronics, and these semiconductors need to feature large-area fabrication, solution processability, high electrical performance, and wide spectral optical absorption properties. Although various strategies of low-temperature-processed n-type semiconductors have been achieved, the development of high-performance p-type semiconductors at low temperature is still limited. Here, we report a unique low-temperature-processed method to synthesize tellurium nanowire networks (Te-nanonets) over a scalable area for the fabrication of high-performance large-area p-type field-effect transistors (FETs) with uniform and stable electrical and optical properties. Maximum mobility of 4.7 cm2/Vs, an on/off current ratio of 1 × 104, and a maximum transconductance of 2.18 µS are achieved. To further demonstrate the applicability of the proposed semiconductor, the electrical performance of a Te-nanonet-based transistor array of 42 devices is also measured, revealing stable and uniform results. Finally, to broaden the applicability of p-type Te-nanonet-based FETs, optical measurements are demonstrated over a wide spectral range, revealing an exceptionally uniform optical performance.

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Large Area Emission in p-Type Polymer-Based Light-Emitting Field-Effect Transistors by Incorporating Charge Injection Interlayers

Materials ◽

10.3390/ma14040901 ◽

2021 ◽

Vol 14 (4) ◽

pp. 901

Author(s):

Gizem Acar ◽

Muhammad Javaid Iqbal ◽

Mujeeb Ullah Chaudhry

Keyword(s):

Field Effect ◽

Field Effect Transistors ◽

Charge Injection ◽

Limiting Factors ◽

Hole Injection ◽

Large Area ◽

Device Structure ◽

Light Emitting ◽

Emission Area ◽

P Type

Organic light-emitting field-effect transistors (LEFETs) provide the possibility of simplifying the display pixilation design as they integrate the drive-transistor and the light emission in a single architecture. However, in p-type LEFETs, simultaneously achieving higher external quantum efficiency (EQE) at higher brightness, larger and stable emission area, and high switching speed are the limiting factors for to realise their applications. Herein, we present a p-type polymer heterostructure-based LEFET architecture with electron and hole injection interlayers to improve the charge injection into the light-emitting layer, which leads to better recombination. This device structure provides access to hole mobility of ~2.1 cm2 V−1 s−1 and EQE of 1.6% at a luminance of 2600 cd m−2. Most importantly, we observed a large area emission under the entire drain electrode, which was spatially stable (emission area is not dependent on the gate voltage and current density). These results show an important advancement in polymer-based LEFET technology toward realizing new digital display applications.

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