scholarly journals Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 454
Author(s):  
You Wang ◽  
Yu Mao ◽  
Qizheng Ji ◽  
Ming Yang ◽  
Zhaonian Yang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Computer Aided Design ◽  
Field Effect ◽  
Electrostatic Discharge ◽  
Field Effect Transistors ◽  
Test Method ◽  
Current Path ◽  
Simulation Results ◽  
Current Characteristics ◽  
Aided Design

Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding.

scholarly journals Investigation on the Hump Behavior of Gate-Normal Nanowire Tunnel Field-Effect Transistors (NWTFETs)

2020 ◽  
Vol 10 (24) ◽  
pp. 8880
Author(s):  
Min Woo Kang ◽  
Woo Young Choi
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Three Dimensional ◽  
Gate Insulator ◽  
Radius Of Curvature ◽  
Computer Aided ◽  
Simulation Results ◽  
Tcad Simulation ◽  
Aided Design

The hump behavior of gate-normal nanowire tunnel field-effect transistors (NWTFETs) is investigated by using a three-dimensional technology computer-aided design (TCAD) simulation. The simulation results show that the hump behavior degrades the subthreshold swing (SS) and on-current (Ion) because the corners and sides of nanowires (NWs) have different surface potentials. The hump behavior can be successfully suppressed by increasing the radius of curvature (R) of NWs and reducing gate insulator thickness (Tins).

Degeneration of Line-Edge Roughness-Induced Variability for Dual-Metal Gate Fin Field-Effect Transistors

2020 ◽  
Vol 15 (1) ◽  
pp. 142-146
Author(s):  
Liang Dai ◽  
Wei-Feng Lü
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Line Edge Roughness ◽  
Metal Gate ◽  
Edge Roughness ◽  
Simulation Results ◽  
Dual Metal ◽  
Aided Design ◽  
First Time

We investigate, for the first time, the effect of line-edge roughness (LER)-induced variability for dual-metal gate (DMG) Fin field-effect transistors (FinFETs) using a computer-aided-design simulation. The Gaussian autocorrelation function is utilized for generating the LER sequence. From the standard deviations of subthreshold swing (SS), threshold voltage (VTH), and transconductance (gm), the simulation results indicate that the LER-induced electrostatic integrity variability is related to the ratio of control gate to total gate lengths. The variability caused by LER degrades with respect to the length of control gate near the source. Our work fills a gap in the study of LER-induced variability for DMG FinFETs, and suggests that the length of the control gate near the source should be greater than or equal to the screen gate near the drain in the entire gate.

scholarly journals Random Dopant Fluctuation-Induced Variability in n-Type Junctionless Dual-Metal Gate FinFETs

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 282 ◽  
Author(s):  
Liang Dai ◽  
Weifeng Lü ◽  
Mi Lin
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Voltage ◽  
Metal Gate ◽  
Random Dopant Fluctuation ◽  
Computer Aided ◽  
Dual Metal ◽  
Aided Design ◽  
Random Dopant

We investigate the effect of random dopant fluctuation (RDF)-induced variability in n-type junctionless (JL) dual-metal gate (DMG) fin field-effect transistors (FinFETs) using a 3D computer-aided design simulation. We show that the drain voltage (VDS) has a significant impact on the electrostatic integrity variability caused by RDF and is dependent on the ratio of gate lengths. The RDF-induced variability also increases as the length of control gate near the source decreases. Our simulations suggest that the proportion of the gate metal near the source to the entire gate should be greater than 0.5.

Si1-yGeyor Ge1-zSnzSource/Drain Stressors on Strained Si1-xGex-Channel P-Type Field-Effect Transistors: A Technology Computer-Aided Design Study

2013 ◽  
Vol 52 (4S) ◽  
pp. 04CC01 ◽  
Author(s):  
Geert Eneman ◽  
An De Keersgieter ◽  
Liesbeth Witters ◽  
Jerome Mitard ◽  
Benjamin Vincent ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Design Study ◽  
Computer Aided ◽  
P Type ◽  
Aided Design

scholarly journals T-Channel Field Effect Transistor with Three Input Terminals (Ti-TcFET)

Micromachines ◽  
2020 ◽  
Vol 11 (1) ◽  
pp. 64
Author(s):  
Zeqi Chen ◽  
Jianping Hu ◽  
Hao Ye ◽  
Zhufei Chu
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Structure Design ◽  
Channel Structure ◽  
Oxide Semiconductor ◽  
Back Gate ◽  
Effect Transistor ◽  
Current Characteristics

In this paper, a novel T-channel field effect transistor with three input terminals (Ti-TcFET) is proposed. The channel of a Ti-TcFET consists of horizontal and vertical sections. The top gate is above the horizontal channel, while the front gate and back gate are on either side of the vertical channel. The T-shaped channel structure increases the coupling area between the top gate and the front and back gates, which improves the ability of the gate electrodes to control the channel. What’s more, it makes the top gate have almost the same control ability for the channel as the front gate and the back gate. This unique structure design brings a unique function in that the device is turned on only when two or three inputs are activated. Silvaco technology computer-aided design (TCAD) simulations are used to verify the current characteristics of the proposed Ti-TcFET. The current characteristics of the device are theoretically analyzed, and the results show that the theoretical analysis agrees with the TCAD simulation results. The proposed Ti-TcFET devices with three input terminals can be used to simplify the complex circuits in a compact style with reduced counts of transistors compared with the traditional complementary metal–oxide–semiconductor/ fin field-effect transistors (CMOS/FinFETs) with a single input terminal and thus provides a new idea for future circuit designs.

scholarly journals A Novel Germanium-Around-Source Gate-All-Around Tunnelling Field-Effect Transistor for Low-Power Applications

Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 164
Author(s):  
Ke Han ◽  
Shanglin Long ◽  
Zhongliang Deng ◽  
Yannan Zhang ◽  
Jiawei Li
Keyword(s):  
Low Power ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Electrical Characteristics ◽  
Source Voltage ◽  
Effect Transistor ◽  
Supply Current ◽  
Aided Design

This paper presents a germanium-around-source gate-all-around tunnelling field-effect transistor (GAS GAA TFET). The electrical characteristics of the device were studied and compared with those of silicon gate-all-around and germanium-based-source gate-all-around tunnel field-effect transistors. Furthermore, the electrical characteristics were optimised using Synopsys Sentaurus technology computer-aided design (TCAD). The GAS GAA TFET contains a combination of around-source germanium and silicon, which have different bandgaps. With an increase in the gate-source voltage, band-to-band tunnelling (BTBT) in silicon rapidly approached saturation since germanium has a higher BTBT probability than silicon. At this moment, germanium could still supply current increment, resulting in a steady and steep average subthreshold swing ( S S AVG ) and a higher ON-state current. The GAS GAA TFET was optimised through work function and drain overlapping engineering. The optimised GAS GAA TFET exhibited a high ON-state current ( I ON ) (11.9 μ A), a low OFF-state current ( I OFF ) ( 2.85 × 10 − 9 μ A), and a low and steady S S AVG (57.29 mV/decade), with the OFF-state current increasing by 10 7 times. The GAS GAA TFET has high potential for use in low-power applications.

Optimizing the Screen-Grid Field Effect Transistor for high drive current and low Miller capacitance

2009 ◽  
Vol 1174 ◽  
Author(s):  
Yasaman Shadrokh ◽  
Kristel Fobelets ◽  
Enrique Velazquez-Perez
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Degrees Of Freedom ◽  
Field Effect Transistors ◽  
Switching Speed ◽  
High Drive ◽  
Gate Control ◽  
Effect Transistor ◽  
Screen Grid ◽  
Aided Design

AbstractReduction of parasitic capacitances and improvement of the on-off current ratio (ION/IOFF) can be achieved by increasing the gate control in Field Effect Transistors (FETs). Multiple gated FETs (MugFETs) lend themselves well for this. The MugFET investigated in this manuscript is the Screen Grid FET (SGrFET) that consists of multiple gate cylinders inside the channel perpendicular to the current flow. In this work we illustrate, using 2D Technology Computer Aided Design (TCAD), that the multiple geometrical degrees of freedom of the SGrFET can be exploited to simultaneously optimise the on-current, ION and the gate-drain Miller parasitic capacitance for increased switching speed.

scholarly journals Design Optimization of Double-Gate Isosceles Trapezoid Tunnel Field-Effect Transistor (DGIT-TFET)

Micromachines ◽  
2019 ◽  
Vol 10 (4) ◽  
pp. 229
Author(s):  
Hwa Gu ◽  
Sangwan Kim
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Channel Structure ◽  
Double Gate ◽  
Ultra Low Power ◽  
Isosceles Trapezoid ◽  
Technical Issues ◽  
Effect Transistor ◽  
Aided Design

Recently, tunnel field-effect transistors (TFETs) have been regarded as next-generation ultra-low-power semi-conductor devices. To commercialize the TFETs, however, it is necessary to improve an on-state current caused by tunnel-junction resistance and to suppress a leakage current from ambipolar current (IAMB). In this paper, we suggest a novel TFET which features double gate, vertical, and trapezoid isosceles channel structure to solve the above-mentioned technical issues. The device design is optimized by examining its electrical characteristics with the help of technology computer-aided design (TCAD) simulation. As a result, double-gate isosceles trapezoid (DGIT) TFET shows a much better performance than the conventional TFET in terms of ON-state current (ION), IAMB, and gate-to-drain capacitance (CGD). It is confirmed that an inverter composed of DGIT-TFETs can operate with less than 1 ns intrinsic delay time and negligible voltage overshoot.

scholarly journals Analysis of Work-Function Variation Effects in a Tunnel Field-Effect Transistor Depending on the Device Structure

2020 ◽  
Vol 10 (15) ◽  
pp. 5378
Author(s):  
Garam Kim ◽  
Jang Hyun Kim ◽  
Jaemin Kim ◽  
Sangwan Kim
Keyword(s):  
Work Function ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Tunneling Current ◽  
Deposition Process ◽  
Device Structure ◽  
Metal Gates ◽  
Grain Distribution ◽  
Aided Design

Metal gate technology is one of the most important methods used to increase the low on-current of tunnel field-effect transistors (TFETs). However, metal gates have different work-functions for each grain during the deposition process, resulting in work-function variation (WFV) effects, which means that the electrical characteristics vary from device to device. The WFV of a planar TFET, double-gate (DG) TFET, and electron-hole bilayer TFET (EHBTFET) were examined by technology computer-aided design (TCAD) simulations to analyze the influences of device structure and to find strategies for suppressing the WFV effects in TFET. Comparing the WFV effects through the turn-on voltage (Vturn-on) distribution, the planar TFET showed the largest standard deviation (σVturn-on) of 20.1 mV, and it was reduced by −26.4% for the DG TFET and −80.1% for the EHBTFET. Based on the analyses regarding metal grain distribution and energy band diagrams, the WFV of TFETs was determined by the number of metal grains involved in the tunneling current. Therefore, the EHBTFET, which can determine the tunneling current by all of the metal grains where the main gate and the sub gate overlap, is considered to be a promising structure that can reduce the WFV effect of TFETs.

scholarly journals The Analysis of SEU in Nanowire FETs and Nanosheet FETs

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 863
Author(s):  
Yunjae Kim ◽  
Myounggon Kang
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Incident Angle ◽  
Three Dimensional ◽  
Design Tools ◽  
Single Event Upset ◽  
Single Event ◽  
The Difference ◽  
Aided Design

The effects of the single-event upset (SEU) generated by radiation on nanowire field-effect transistors (NW-FETs) and nanosheet (NS)-FETs were analyzed according to the incident angle and location of radiation, by using three-dimensional technology computer-aided design tools. The greatest SEU occurred when the particle was incident at 90°, whereas the least occurred at 15°. SEU was significantly affected when the particle was incident on the drain, as compared to when it was incident on the source. The NS-FETs were robust to SEU, unlike the NW-FETs. This phenomenon can be attributed to the difference in the area exposed to radiation, even if the channel widths of these devices were identical.

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