Differential Low Noise Amplifier for S-Band Phased-Array Radar in 0.18-µm CMOS Technology

2019 ◽  
Author(s):  
Tzu-Yu Hsia ◽  
Xin-Yi Li ◽  
Liang-Yu Ou Yang ◽  
Zuo-Min Tsai ◽  
Shih-Yuan Chen
Keyword(s):  
Phased Array ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Phased Array Radar ◽  
Noise Amplifier

scholarly journals A 0.18um CMOS Low Noise Amplifier for 3-5ghz UWB Receivers

2018 ◽  
Vol 7 (3.6) ◽  
pp. 84
Author(s):  
N Malika Begum ◽  
W Yasmeen
Keyword(s):  
Power Supply ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Noise Amplifier ◽  
5 Ghz ◽  
Chebyshev Filter ◽  
Minimum Noise

This paper presents an Ultra-Wideband (UWB) 3-5 GHz Low Noise Amplifier (LNA) employing Chebyshev filter. The LNA has been designed using Cadence 0.18um CMOS technology. Proposed LNA achieves a minimum noise figure of 2.2dB, power gain of 9dB.The power consumption is 6.3mW from 1.8V power supply.  

scholarly journals A 2.4 GHz low noise amplifier design at 130nm CMOS technology using common gate topology for WiFi / WiMAX application

2017 ◽  
Vol 7 (1.3) ◽  
pp. 69
Author(s):  
M. Ramana Reddy ◽  
N.S Murthy Sharma ◽  
P. Chandra Sekhar
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Low Power Consumption ◽  
Common Gate ◽  
Chip Size ◽  
Overall Performance ◽  
Amplifier Design ◽  
Noise Amplifier

The proposed work shows an innovative designing in TSMC 130nm CMOS technology. A 2.4 GHz common gate topology low noise amplifier (LNA) using an active inductor to attain the low power consumption and to get the small chip size in layout design. By using this Common gate topology achieves the noise figure of 4dB, Forward gain (S21) parameter of 14.7dB, and the small chip size of 0.26 mm, while 0.8mW power consuming from a 1.1V in 130nm CMOS gives the better noise figure and improved the overall performance.

scholarly journals CMOS Ultra-Wideband Low Noise Amplifier Design

2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
K. Yousef ◽  
H. Jia ◽  
R. Pokharel ◽  
A. Allam ◽  
M. Ragab ◽  
...  
Keyword(s):  
Impedance Matching ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Output Impedance ◽  
Integrated Inductor ◽  
Technology Process ◽  
Amplifier Design ◽  
Noise Amplifier

This paper presents the design of ultra-wideband low noise amplifier (UWB LNA). The proposed UWB LNA whose bandwidth extends from 2.5 GHz to 16 GHz is designed using a symmetric 3D RF integrated inductor. This UWB LNA has a gain of 11 ± 1.0 dB and a NF less than 3.3 dB. Good input and output impedance matching and good isolation are achieved over the operating frequency band. The proposed UWB LNA is driven from a 1.8 V supply. The UWB LNA is designed and simulated in standard TSMC 0.18 µm CMOS technology process.

scholarly journals Design of Low Power UWB CMOS Low Noise Amplifier using Active Inductor for WLAN Receiver

2018 ◽  
Vol 7 (2.24) ◽  
pp. 448
Author(s):  
S Manjula ◽  
M Malleshwari ◽  
M Suganthy
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Wide Band ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Design System ◽  
Active Inductor ◽  
Chip Area ◽  
Noise Amplifier

This paper presents a low power Low Noise Amplifier (LNA) using 0.18µm CMOS technology for ultra wide band (UWB) applications. gm boosting common gate (CG) LNA is designed to improve the noise performance.  For the reduction of on chip area, active inductor is employed at the input side of the designed LNA for input impedance matching. The proposed UWB LNA is designed using Advanced Design System (ADS) at UWB frequency of 3.1-10.6 GHz. Simulation results show that the gain of 10.74+ 0.01 dB, noise figure is 4.855 dB, input return loss <-13 dB and 12.5 mW power consumption.  

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