A novel methodology to combine and speed-up the verification process of simulation and measurement of integrated circuits

Author(s):  
Anton Pirker-Fruhauf ◽  
Matthias Kunze
2021 ◽  
Vol 5 (1) ◽  
pp. 129
Author(s):  
Eldy Dwi Sentosa ◽  
Iskandar Fitri ◽  
Agus Iskandar

The system for viewing student seminar payment data can be viewed through administrator controls. The seminar payment confirmation process for National University students still uses the manual system by paying the seminar organizer so it takes longer to process the seminar payment. The purpose of creating this system is to speed up the payment time of the seminar. This system uses a unique 3-digit code in each payment of seminar participants, this unique 3-digit code acts as a mark that differentiates student payments so that it does not require confirmation to the seminar organizer. Cron work will be performed on UNIX-based operating systems (Linux, Ubuntu, etc.) which function to perform tasks or scripts automatically. The content of the script is an order to execute the payment confirmation order against the participant. This level of research consists of several stages, namely needs analysis, design, writing system application code, application testing. This investigation has resulted in an application that can expedite the payment verification process by matching the number of transfer participants with those in the database. The results of testing the payment verification process are influenced by the Crawl Algorithm to help the payment process become more effective. With results that have been tested on average, it shows 4.8 seconds to confirm the participant's payment. With this seminar payment system, you can save time to process seminar payments.


2021 ◽  
Vol 3 (3) ◽  
pp. 255-268
Author(s):  
Yasir Babiker Hamdan ◽  
A. Sathesh

Voting is now governed by regulations that specify how a person's choices may be communicated and their desires can be realized. This study proposes an electronic voting machine (EVM) as an alternative for traditional voting methods, which may include the manual utilization of only microcontroller-based circuits. With the identified fingerprint liveness, the proposed technique will make voting considerably easier, more effective, and less likely to result in fraud. The suggested model will support and advance the trustworthiness of all votes and it will also assist in streamlining the counting and verification process. It is difficult to demonstrate that an advanced voting system has been properly designed since several critical criteria must be satisfied. Poll results should be kept private in the database in order to preserve the data. The voting process must also show the votes obtained by the respective candidates. The proposed authenticated voting machine can be applied to the local area elections in order to speed up the process and make the election process more transparent. To maintain its theoretical strength, the proposed research idea needs further study. The model employs radio frequency and fingerprint recognition to maintain the protection.


2014 ◽  
Vol 909 ◽  
pp. 397-404
Author(s):  
N.S.S. Singh ◽  
N.H. Hamid ◽  
V.S. Asirvadam

With the continuous scaling of CMOS technology, reliability of nanobased electronic circuits is endlessly becoming a major concern. Due to this phenomenon, several computational approaches have been developed for the reliability assessment of modern logic integrated circuits. However, these analytical methodologies have a computational complexity that increases exponentially with the circuit dimension, making the whole reliability assessment process of large circuits becoming very time consuming and intractable. Therefore, to speed up the reliability assessment of large circuits, this paper firstly looks into the development of a programmed reliability tool. The Matlab-based tool is developed based on the generalization of Probabilistic Transfer Matrix (PTM) model as one of the existing reliability assessment approaches. Users have to provide description of the desired circuit in the form of Netlist that becomes the input to the programmed tool. For illustration purpose, in this paper, C17 has been used as the benchmark test circuit for its reliability computation. Secondly, reliability of a desired circuit does not only depend on its faulty gates, but it also depends on the maximum error threshold of these faulty gates above which no reliable computation is possible. For this purpose, the developed tool is employed again to find the exact error thresholds for faulty gates.


2012 ◽  
Vol 19 (2) ◽  
pp. 191-202
Author(s):  
Waldemar Jendernalik ◽  
Jacek Jakusz ◽  
Grzegorz Blakiewicz ◽  
Stanisław Szczepański ◽  
Robert Piotrowski

Characteristics of an Image Sensor with Early-Vision Processing Fabricated in Standard 0.35 μm Cmos TechnologyThe article presents measurement results of prototype integrated circuits for acquisition and processing of images in real time. In order to verify a new concept of circuit solutions of analogue image processors, experimental integrated circuits were fabricated. The integrated circuits, designed in a standard 0.35 μm CMOS technology, contain the image sensor and analogue processors that perform low-level convolution-based image processing algorithms. The prototype with a resolution of 32 × 32 pixels allows the acquisition and processing of images at high speed, up to 2000 frames/s. Operation of the prototypes was verified in practice using the developed software and a measurement system based on a FPGA platform.


Author(s):  
Abhilash M H ◽  
Amberker B B

Revocation is an important feature of group signature schemes. Verifier Local Revocation (VLR) is a popular revocation mechanism which involves only verifiers in the revocation process. In VLR, a revocation list is maintained to store the information about revoked users. The verification cost of VLR based schemes islinearly proportional to the size of recvocation list. In many applications, the size of revocation list grows with time, which makes the verification process expensive. In this paper, we propose a lattice based dynamic group signature using VLR and time bound keys to reduce the size of revocation list to speed up the verification process. In the proposed scheme, an expiration date is fixed for signing key of each group member, and verifiers can find out (at constantcost) if a signature is generated using an expired key. Hence revocation information of members who are revoked before signing key expiry date (premature revocation) are kept in revocation list, and other members are part of natural revocation. This leads to a significant saving on the revocation check by assuming natural revocation accounts for large fraction of the total revocation. This scheme also takes care of non-forgeability of signing key expiry date.


2019 ◽  
Vol 11 (8) ◽  
pp. 167 ◽  
Author(s):  
Saumendra Sengupta ◽  
Chen-Fu Chiang ◽  
Bruno Andriamanalimanana ◽  
Jorge Novillo ◽  
Ali Tekeoglu

Latency is a critical issue that impacts the performance of decentralized systems. Recently we designed various protocols to regulate the injection rate of unverified transactions into the system to improve system performance. Each of the protocols is designed to address issues related to some particular network traffic syndrome. In this work, we first provide the review of our prior protocols. We then provide a hybrid scheme that combines our transaction injection protocols and provides an optimal linear combination of the protocols based on the syndromes in the network. The goal is to speed up the verification process of systems that rely on only one single basic protocol. The underlying basic protocols are Periodic Injection of Transaction via Evaluation Corridor (PITEC), Probabilistic Injection of Transactions (PIT), and Adaptive Semi-synchronous Transaction Injection (ASTI).


Author(s):  
Emil Benedykciuk ◽  
Marcin Denkowski ◽  
Krzysztof Dmitruk

AbstractSecurity X-ray baggage scanners provide images based on the different levels of radiation absorption by different materials. Images captured by such scanners are inspected by a human operator, which can slow down the verification process. To speed up inspection time, computer vision and machine learning methods are increasingly being used. While object recognition has been the subject of a huge number of articles, the problem of material recognition in X-ray images still requires some work to achieve equivalent accuracy. This paper focuses on the problem of discrimination of materials into several classes, such as organic substances or metals, in images obtained from dual-energy X-ray security scanners. We propose a new multi-scale convolutional neural network (CNN) for predicting the material class, in which five different sizes of patches are implemented parallelly to balance the trade-off between the increase in the receptive field and the loss of detail. We analyze some regularization methods and activation functions and their impact on the effectiveness of our architecture. The results were compared with other popular CNN architectures and demonstrate the superiority of our solution.


Author(s):  
Michael D. Capili

Driven by the company vision to become a high-volume manufacturing (HVM), increasing throughput in the manufacturing line is critical to meeting market demands. The ever-growing demand for integrated circuits in part requires additional capital investment to purchase new equipment such as die bonders to support the new requirement. Making the best of existing resources is often the most common approach to deal with this challenge. Defining the correct method and making the most of the secondary parameters necessary to increase the bonding speed by means of a creative analysis that made this article interesting. The objective of this project is to boost productivity by maximizing UPH to improve the epoxy writing process at Attach, which is a bottleneck area. Optimization of the dispensing sequence and the dispensing direction to improve and speed up the epoxy dispensing process unit per hour.


2021 ◽  
Vol 2021 ◽  
pp. 1-13
Author(s):  
Zeeshan Raza ◽  
Irfan ul Haq ◽  
Muhammad Muneeb ◽  
Omair Shafiq

Blockchain as a decentralized distributed ledger is revolutionizing the world with a secure design data storage mechanism. In the case of Bitcoin, mining involves a process of packing transactions in a block by calculating a random number termed as a nonce. The nonce calculation is done by special nodes called miners, and all the miners follow the Proof of Work (PoW) mining mechanism to perform the mining task. The transaction verification time in PoW-based blockchain systems, i.e., Bitcoin, is much slower than other digital transaction systems such as PayPal. It needs to be quicker if a system adapts PoW-based blockchain solutions, where there are thousands of transactions being computed at a time. Besides this, PoW mining also consumes a lot of energy to calculate the nonce of a block. Mining pools resulting into aggregated hashpower have been a popular solution to speed up the PoW mining, but they can be attacked by using different types of attacks. Parallel computing can be used to speed up the solo mining methods by utilizing the multiple processes of the contributing processors. In this research, we analyze various consensus mechanisms and see that the PoW-based blockchain systems have the limitations of low transaction confirmation time and high energy consumption. We also analyze various types of consensus layer attacks and their effects on miners and mining pools. To tackle these issues, we propose parallel PoW nonce calculation methods to accelerate the transaction verification process especially in solo mining. We have tested our techniques on different difficulty levels, and our proposed techniques yield better results than the traditional nonce computation mechanisms.


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