Physical modeling and alleviation of shallow trench-isolation charging effects in silicon-on insulator complementary bipolar technology

Author(s):  
W. Yindeepol ◽  
R. Foote ◽  
J. De Santis ◽  
T. Krakowski ◽  
C. Bulucea
1999 ◽  
Vol 566 ◽  
Author(s):  
Thomas H. Osterheld ◽  
Steve Zuniga ◽  
Sidney Huey ◽  
Peter McKeever ◽  
Chad Garretson ◽  
...  

This paper reports a technological advancement in developing and implementing a novel retaining ring of advanced edge performance (AEPTM ring) for an advanced polishing head design. The AEP ring has been successfully used for significantly improved CMP performance in different CMP applications: oxide (PMD and ILD), shallow trench isolation (STI), polysilicon, metal (W and Cu), silicon-on-insulator (SOI), and silicon CMP. Robust processes have been developed using AEP ring along with many hardware upgrades for each application with extended runs to meet requirements of advanced IC device fabrication.


2005 ◽  
Vol 108-109 ◽  
pp. 439-444
Author(s):  
Helene Bourdon ◽  
Claire Fenouillet-Béranger ◽  
Claire Gallon ◽  
Philippe Coronel ◽  
Damien Lenoble

The fully depleted SOI devices present lateral isolation issues due to the shallow trench isolation (STI) process. We propose in this paper to study a new fabrication process for integrating local isolation trenches. Germanium (Ge) implantation is used to create SiGe (Silicon-Germanium) layer on thin SOI (silicon on insulator) that can be selectively etched. The advantage is the capability of implantation to localize the SiGe area on this substrate and to avoid STI process issues. Aggressive dimensions and geometries are studied and resulting material transformation (crystallization and Ge diffusion) are apprehending via SEM (Secondary Electron Microscopy) or AFM (Atomic Force Spectroscopy) to understand the etching kinetics. After optimization, we demonstrate the capability of fabricating localized trenches on SOI without degrading the neighboring Si layer or consuming the thin BOX (buried oxide).


2002 ◽  
Vol 40 (4) ◽  
pp. 653 ◽  
Author(s):  
Lee Hyeokjae ◽  
Park Young June ◽  
Min Hong Shick ◽  
Lee Jong Ho ◽  
Shin Hyungsoon ◽  
...  

1998 ◽  
Author(s):  
I. De Wolf ◽  
G. Groeseneken ◽  
H.E. Maes ◽  
M. Bolt ◽  
K. Barla ◽  
...  

Abstract It is shown, using micro-Raman spectroscopy, that Shallow Trench Isolation introduces high stresses in the active area of silicon devices when wet oxidation steps are used. These stresses result in defect formation in the active area, leading to high diode leakage currents. The stress levels are highest near the outer edges of line structures and at square structures. They also increase with decreasing active area dimensions.


MRS Bulletin ◽  
2002 ◽  
Vol 27 (10) ◽  
pp. 743-751 ◽  
Author(s):  
Rajiv K. Singh ◽  
Rajeev Bajaj

AbstractThe primary aim of this issue of MRS Bulletin is to present an overview of the materials issues in chemical–mechanical planarization (CMP), also known as chemical–mechanial polishing, a process that is used in the semiconductor industry to isolate and connect individual transistors on a chip. The CMP process has been the fastest-growing semiconductor operation in the last decade, and its future growth is being fueled by the introduction of copper-based interconnects in advanced microprocessors and other devices. Articles in this issue range from providing a fundamental understanding of the CMP process to the latest advancements in the field. Topics covered in these articles include an overview of CMP, fundamental principles of slurry design, understanding wafer–pad–slurry interactions, process integration issues, the formulation of abrasive-free slurries for copper polishing, understanding surface topography issues in shallow trench isolation, and emerging applications.


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