A Novel Retaining Ring in Advanced Polishing Head Design for Significantly Improved CMP Performance

1999 ◽  
Vol 566 ◽  
Author(s):  
Thomas H. Osterheld ◽  
Steve Zuniga ◽  
Sidney Huey ◽  
Peter McKeever ◽  
Chad Garretson ◽  
...  
Keyword(s):  
Device Fabrication ◽  
Silicon On Insulator ◽  
Technological Advancement ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Retaining Ring

This paper reports a technological advancement in developing and implementing a novel retaining ring of advanced edge performance (AEPTM ring) for an advanced polishing head design. The AEP ring has been successfully used for significantly improved CMP performance in different CMP applications: oxide (PMD and ILD), shallow trench isolation (STI), polysilicon, metal (W and Cu), silicon-on-insulator (SOI), and silicon CMP. Robust processes have been developed using AEP ring along with many hardware upgrades for each application with extended runs to meet requirements of advanced IC device fabrication.

Selective SiGe Etching Formed by Localized Ge Implantation on SOI

2005 ◽  
Vol 108-109 ◽  
pp. 439-444
Author(s):  
Helene Bourdon ◽  
Claire Fenouillet-Béranger ◽  
Claire Gallon ◽  
Philippe Coronel ◽  
Damien Lenoble
Keyword(s):  
Electron Microscopy ◽  
Silicon Germanium ◽  
Secondary Electron ◽  
Silicon On Insulator ◽  
Shallow Trench Isolation ◽  
Fully Depleted ◽  
Atomic Force ◽  
Trench Isolation ◽  
Germanium Layer ◽  
Soi Devices

The fully depleted SOI devices present lateral isolation issues due to the shallow trench isolation (STI) process. We propose in this paper to study a new fabrication process for integrating local isolation trenches. Germanium (Ge) implantation is used to create SiGe (Silicon-Germanium) layer on thin SOI (silicon on insulator) that can be selectively etched. The advantage is the capability of implantation to localize the SiGe area on this substrate and to avoid STI process issues. Aggressive dimensions and geometries are studied and resulting material transformation (crystallization and Ge diffusion) are apprehending via SEM (Secondary Electron Microscopy) or AFM (Atomic Force Spectroscopy) to understand the etching kinetics. After optimization, we demonstrate the capability of fabricating localized trenches on SOI without degrading the neighboring Si layer or consuming the thin BOX (buried oxide).

Effects of Shallow Trench Isolation on Silicon-on-Insulator Devices for Mixed Signal Processing

2002 ◽  
Vol 40 (4) ◽  
pp. 653 ◽  
Author(s):  
Lee Hyeokjae ◽  
Park Young June ◽  
Min Hong Shick ◽  
Lee Jong Ho ◽  
Shin Hyungsoon ◽  
...  
Keyword(s):  
Signal Processing ◽  
Silicon On Insulator ◽  
Shallow Trench Isolation ◽  
Mixed Signal ◽  
Trench Isolation

Heat and Mass Transport in HDP-CVD Chamber

2003 ◽  
Author(s):  
Hemant Mungekar ◽  
Bruno Geoffrion ◽  
Bikram Kapoor ◽  
Naren Dubey ◽  
Mak Salimian ◽  
...  
Keyword(s):  
Heat Transfer ◽  
Mass Transfer ◽  
Aspect Ratio ◽  
State Of The Art ◽  
Memory Device ◽  
Device Fabrication ◽  
Shallow Trench Isolation ◽  
Heat And Mass Transport ◽  
Trench Isolation ◽  
Plasma Facing Materials

HDP-CVD reactors are used for Shallow Trench Isolation (STI), Inter Metal Dielectric (IMD) and Inter Layer Dielectric (ILD) applications for logic and memory device fabrication. As device dimension shrinks, the trend has been to use lower pressure and higher plasma density for gap-fill with higher aspect ratio (AR). Higher AR gapfill in addition to higher throughput is achieved by running multiple wafers between a chamber clean, present a unique set of challenges for heat and mass-transfer in an HDP-CVD reactor. This paper describes some of the new state-of-the-art hardware innovations specifically developed to meet these challenges. In particular, heat transfer to plasma facing materials, fluid mechanics, and transport of sub-micron sized particles in the plasma environment of an HDP-CVD reactor are explored.

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

Analysis of Silicon-On-Insulator Structures Formed By Oxygen Ion Implantation

1985 ◽  
Vol 43 ◽  
pp. 300-301
Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
A. Mogro-Campero ◽  
R. P. Love
Keyword(s):  
Ion Implantation ◽  
Single Crystal ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Dose ◽  
Crystal Silicon ◽  
Oxygen Ion ◽  
Oxygen Ion Implantation

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

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