Evaluating Coverage of Error Detection Logic for Soft Errors using Formal Methods

2006 ◽  
Author(s):  
U. Krautz ◽  
M. Pflanz ◽  
C. Jacobi ◽  
H.W. Tast ◽  
K. Weber ◽  
...  
Keyword(s):  
Formal Methods ◽  
Error Detection ◽  
Soft Errors

scholarly journals Optimized switch-level soft error detection based on advanced switch-level models

2021 ◽  
Author(s):  
Jalal Mohammad Chikhe
Keyword(s):  
Error Detection ◽  
Early Stage ◽  
Soft Errors ◽  
Logic Gate ◽  
Soft Error ◽  
Combinational Circuits ◽  
Single Event Transient ◽  
New Techniques ◽  
Speed Up ◽  
Logic Threshold

Due to the reduction of transistor size, modern circuits are becoming more sensitive to soft errors. The development of new techniques and algorithms targeting soft error detection are important as they allow designers to evaluate the weaknesses of the circuits at an early stage of the design. The project presents an optimized implementation of soft error detection simulator targeting combinational circuits. The developed simulator uses advanced switch level models allowing the injection of soft errors caused by single event-transient pulses with magnitudes lesser than the logic threshold. The ISCAS'85 benchmark circuits are used for the simulations. The transients can be injected at drain, gate, or inputs of logic gate. This gives clear indication of the importance of transient injection location on the fault coverage. Furthermore, an algorithm is designed and implemented in this work to increase the performance of the simulator. This optimized version of the simulator achieved an average speed-up of 310 compared to the non-algorithm based version of the simulator.

scholarly journals An Investigation into Soft Error Detection Efficiency at Operating System Level

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Seyyed Amir Asghari ◽  
Okyay Kaynak ◽  
Hassan Taheri
Keyword(s):  
Operating System ◽  
Error Detection ◽  
Detection Efficiency ◽  
Soft Errors ◽  
Control Flow ◽  
Soft Error ◽  
System Level ◽  
Occurrence Rate ◽  
Transient Errors ◽  
System Components

Electronic equipment operating in harsh environments such as space is subjected to a range of threats. The most important of these is radiation that gives rise to permanent and transient errors on microelectronic components. The occurrence rate of transient errors is significantly more than permanent errors. The transient errors, or soft errors, emerge in two formats: control flow errors (CFEs) and data errors. Valuable research results have already appeared in literature at hardware and software levels for their alleviation. However, there is the basic assumption behind these works that the operating system is reliable and the focus is on other system levels. In this paper, we investigate the effects of soft errors on the operating system components and compare their vulnerability with that of application level components. Results show that soft errors in operating system components affect both operating system and application level components. Therefore, by providing endurance to operating system level components against soft errors, both operating system and application level components gain tolerance.

scholarly journals DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA

Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 122
Author(s):  
Jiemin Li ◽  
Shancong Zhang ◽  
Chong Bao
Keyword(s):  
Error Detection ◽  
Integrated Circuit ◽  
Large Scale ◽  
Fault Tolerant ◽  
Soft Errors ◽  
Implementation Process ◽  
Radiation Environment ◽  
Cmos Integrated Circuit ◽  
Processor Core ◽  
The Impact

With the development of large-scale CMOS-integrated circuit manufacturing technology, microprocessor chips are more vulnerable to soft errors and radiation interference, resulting in reduced reliability. Core reliability is an important element of the microprocessor’s ability to resist soft errors. This paper proposes DuckCore, a fault-tolerant processor core architecture based on the free and open instruction set architecture (ISA) RISC-V. This architecture uses improved SECDED (single error correction, double error detection) code between pipelines, detects processor operating errors in real-time through the Supervision unit, and takes instruction rollbacks for different error types, which not only saves resources but also improves the reliability of the processor core. In the implementation process, all error injection tests are passed to verify the completeness of the function. In order to better verify the performance of the processor under different error intensity injections, the software is used to inject errors, the running program is run on the FPGA (Field Programmable Gate Array), and the impact of the actual radiation environment on the architecture is evaluated through the results. The architecture is applied to three–five-stage open-source processor cores and the results show that this method consumes fewer resources and its discrete design makes it more portable.

Full Error Detection and Correction Method Applied on Pipelined Structure Using Two Approaches

2020 ◽  
Vol 29 (13) ◽  
pp. 2050218 ◽  
Author(s):  
Mehmed Dug ◽  
Stefan Weidling ◽  
Egor Sogomonyan ◽  
Dejan Jokic ◽  
Milos Krstic
Keyword(s):  
Error Detection ◽  
Soft Errors ◽  
Correction Method ◽  
Soft Error ◽  
Combinational Logic ◽  
Combinational Circuit ◽  
Multiple Faults ◽  
Error Detection And Correction ◽  
Detection Circuit ◽  
The One

In this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multiple faults created at the output of combinational circuit. On the other hand, the FDC approach leads to higher power consumption and area increase compared to the CCPP approach.

scholarly journals Robust Face Recognition Against Soft-errors Using a Cross-layer Approach

2016 ◽  
Vol 11 (5) ◽  
pp. 657
Author(s):  
Gu-Min Jeong ◽  
Chang-Woo Park ◽  
Sang-Il Choi ◽  
Kyoungwoo Lee ◽  
Nikil Dutt
Keyword(s):  
Face Recognition ◽  
Embedded System ◽  
Error Detection ◽  
Soft Errors ◽  
Memory Systems ◽  
Recognition System ◽  
Soft Error ◽  
Multimedia Systems ◽  
Cross Layer ◽  
Robust Face Recognition

Recently, soft-errors, temporary bit toggles in memory systems, have become increasingly important. Although soft-errors are not critical to the stability of recognition systems or multimedia systems, they can significantly degrade the system performance. Considering these facts, in this paper, we propose a novel method for robust face recognition against soft-errors using a cross layer approach. To attenuate the effect of soft-errors in the face recognition system, they are detected in the embedded system layer by using a parity bit checker and compensated in the application layer by using a mean face. We present the soft-error detection module for face recognition and the compensation module based on the mean face of the facial images. Simulation results show that the proposed system effectively compensates for the performance degradation due to soft errors and improves the performance by 2.11 % in case of the Yale database and by 10.43 % in case of the ORL database on average as compared to that with the soft-errors induced.

scholarly journals Generic Methodology for Formal Verification of UML Models

2022 ◽  
Vol 72 (1) ◽  
pp. 40-48
Author(s):  
K.H. Kochaleema ◽  
G. Santhosh Kumar
Keyword(s):  
Software Development ◽  
Embedded System ◽  
Formal Verification ◽  
Formal Methods ◽  
Error Detection ◽  
Formal Model ◽  
Early Error ◽  
Verification Process ◽  
Property Verification ◽  
Uml Models

This paper discusses a Unified Modelling Language (UML) based formal verification methodology for early error detection in the model-based software development cycle. Our approach proposes a UML-based formal verification process utilising functional and behavioural modelling artifacts of UML. It reinforces these artifacts with formal model transition and property verification. The main contribution is a UML to Labelled Transition System (LTS) Translator application that automatically converts UML Statecharts to formal models. Property specifications are derived from system requirements and corresponding Computational Tree Logic (CTL)/Linear Temporal Logic (LTL) model checking procedure verifies property entailment in LTS. With its ability to verify CTL and LTL specifications, the methodology becomes generic for verifying all types of embedded system behaviours. The steep learning curve associated with formal methods is avoided through the automatic formal model generation and thus reduces the reluctance of using formal methods in software development projects. A case study of an embedded controller used in military applications validates the methodology. It establishes how the methodology finds its use in verifying the correctness and consistency of UML models before implementation.

scholarly journals Fault Detection For ASIC Design Reliability On Resistive Delay Faults And Strength-Based Soft-Errors

2021 ◽  
Author(s):  
Mohammad R.S. Javaheri
Keyword(s):  
Error Detection ◽  
High Speed ◽  
Soft Errors ◽  
Error Rates ◽  
Soft Error ◽  
Delay Faults ◽  
Fault Propagation ◽  
Delay Fault ◽  
Wide Range ◽  
Strength Based

Soft-errors (SEs) and delay faults (DFs) frequently occur in modern high-density, high-speed, low-power VLSI circuits. Therefore, SE hardened design and DF testing are essential. This thesis introduces two novel methods for soft-error detection and delay fault propagation in nanometre technology. A new idea is proposed to propagate those delay faults that are not causing logic failure at the site of the defect, but the delay makes the circuit more prone to soft-errors that manifest the effect of delay faults. This approach propagates the fault from the fault location by mapping a nine-valued voltage model on top of a five-valued voltage model to convert delay faults to static faults. This original idea reduces the complexity of delay fault propagation. This thesis introduces an original approach toward soft-error detection based on the strength violation in the circuit. This research shows that transient pulses of less than threshold voltage will cause soft-errors without altering the logic value at the strike location. This method will increase the Soft-Error Rates (SER) for all existing methods if strength-based Soft-Error detection will be considered. The offered approach uses a novel coding system that carries both logic and strength which applies to certain logic functions that are sensitive to strength variations. A wide range of soft-errors are the result of strength violation in switch-level that have never been investigated before.

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