scholarly journals DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA

Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 122
Author(s):  
Jiemin Li ◽  
Shancong Zhang ◽  
Chong Bao
Keyword(s):  
Error Detection ◽  
Integrated Circuit ◽  
Large Scale ◽  
Fault Tolerant ◽  
Soft Errors ◽  
Implementation Process ◽  
Radiation Environment ◽  
Cmos Integrated Circuit ◽  
Processor Core ◽  
The Impact

With the development of large-scale CMOS-integrated circuit manufacturing technology, microprocessor chips are more vulnerable to soft errors and radiation interference, resulting in reduced reliability. Core reliability is an important element of the microprocessor’s ability to resist soft errors. This paper proposes DuckCore, a fault-tolerant processor core architecture based on the free and open instruction set architecture (ISA) RISC-V. This architecture uses improved SECDED (single error correction, double error detection) code between pipelines, detects processor operating errors in real-time through the Supervision unit, and takes instruction rollbacks for different error types, which not only saves resources but also improves the reliability of the processor core. In the implementation process, all error injection tests are passed to verify the completeness of the function. In order to better verify the performance of the processor under different error intensity injections, the software is used to inject errors, the running program is run on the FPGA (Field Programmable Gate Array), and the impact of the actual radiation environment on the architecture is evaluated through the results. The architecture is applied to three–five-stage open-source processor cores and the results show that this method consumes fewer resources and its discrete design makes it more portable.

scholarly journals Architecture and Design of a Spiking Neuron Processor Core Towards the Design of a Large-scale Event-Driven 3D-NoC-based Neuromorphic Processor

2020 ◽  
Vol 77 ◽  
pp. 04003
Author(s):  
Mark Ogbodo ◽  
Khanh Dang ◽  
Fukuchi Tomohide ◽  
Abderazek Abdallah
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Fault Tolerant ◽  
Three Dimensional ◽  
Spiking Neuron ◽  
Chip Area ◽  
Processor Core ◽  
Neuromorphic Systems ◽  
Event Driven ◽  
On Chip

Neuromorphic computing tries to model in hardware the biological brain which is adept at operating in a rapid, real-time, parallel, low power, adaptive and fault-tolerant manner within a volume of 2 liters. Leveraging the event driven nature of Spiking Neural Network (SNN), neuromorphic systems have been able to demonstrate low power consumption by power gating sections of the network not driven by an event at any point in time. However, further exploration in this field towards the building of edge application friendly agents and efficient scalable neuromorphic systems with large number of synapses necessitates the building of small-sized low power spiking neuron processor core with efficient neuro-coding scheme and fault tolerance. This paper presents a spiking neuron processor core suitable for an event-driven Three-Dimensional Network on Chip (3D-NoC) SNN based neuromorphic systems. The spiking neuron Processor core houses an array of leaky integrate and fire (LIF) neurons, and utilizes a crossbar memory in modelling the synapses, all within a chip area of 0.12mm2 and was able to achieves an accuracy of 95.15% on MNIST dataset inference.

'Paris rules' will drive global climate progress

2016 ◽  
Keyword(s):  
Climate Change ◽  
Large Scale ◽  
Global Climate ◽  
National Level ◽  
Implementation Process ◽  
Peer Pressure ◽  
Content Type ◽  
Climate Change Effects ◽  
Growth Prospects ◽  
The Impact

Significance COP22 has been dubbed "the COP of action, adaptation and Africa". It is a key opportunity to build confidence in the system of global cooperation adopted at the Paris Climate Conference. The Paris meeting ushered in a new framework for cooperation on climate change based on voluntary emissions reductions targets that will be jointly reviewed every five years. Negotiators gathering in Marrakech for COP22 face the task of making the Paris Agreement work -- and delivering results on a sufficiently large scale. Impacts Cooperation under the Paris framework will help reduce climate change effects, though overshooting of the 2 degree target is inevitable. The Paris deal's reliance on peer pressure and self-policing will risk national-level backsliding during the implementation process. Actions taken in the next ten years will determine the impact of climate change on global growth prospects for the whole of this century.

scholarly journals A Self-Checking Hardware Journal for a Fault-Tolerant Processor Architecture

2011 ◽  
Vol 2011 ◽  
pp. 1-15 ◽  
Author(s):  
Mohsin Amin ◽  
Abbas Ramazani ◽  
Fabrice Monteiro ◽  
Camille Diou ◽  
Abbas Dandache
Keyword(s):  
Fault Tolerance ◽  
Error Detection ◽  
Error Control ◽  
Fault Tolerant ◽  
Error Rates ◽  
Main Memory ◽  
Transient Faults ◽  
Processor Core ◽  
Detection Techniques ◽  
Performance Area

We introduce a specialized self-checking hardware journal being used as a centerpiece in our design strategy to build a processor tolerant to transient faults. Fault tolerance here relies on the use of error detection techniques in the processor core together with journalization and rollback execution to recover from erroneous situations. Effective rollback recovery is possible thanks to using a hardware journal and chosing a stack computing architecture for the processor core instead of the usual RISC or CISC. The main objective of the journalization and the hardware self-checking journal is to prevent data not yet validated to be sent to the main memory, and allow to fast rollback execution on faulty situations. The main memory, supposed to be fault secure in our model, only contains valid (uncorrupted) data obtained from fault-free computations. Error control coding techniques are used both in the processor core to detect errors and in the HW journal to protect the temporarily stored data from possible changes induced by transient faults. Implementation results on an FPGA of the Altera Stratix-II family show clearly the relevance of the approach, both in terms of performance/area tradeoff and fault tolerance effectiveness, even for high error rates.

scholarly journals SEDAR: Soft Error Detection and Automatic Recovery in High Performance Computing Systems

2020 ◽  
Vol 20 (2) ◽  
pp. e14
Author(s):  
Diego Montezanti
Keyword(s):  
Fault Tolerance ◽  
Error Detection ◽  
Large Scale ◽  
Soft Error ◽  
Scientific Applications ◽  
Case Scenario ◽  
Worst Case ◽  
Main Challenge ◽  
Increased Risk ◽  
The Impact

  Reliability and fault tolerance have become aspects of growing relevance in the field of HPC, due to the increased probability that faults of different kinds will occur in these systems. This is fundamentally due to the increasing complexity of the processors, in the search to improve performance, which leads to a rise in the scale of integration and in the number of components that work near their technological limits, being increasingly prone to failures. Another factor that affects is the growth in the size of parallel systems to obtain greater computational power, in terms of number of cores and processing nodes. As applications demand longer uninterrupted computation times, the impact of faults grows, due to the cost of relaunching an execution that was aborted due to the occurrence of a fault or concluded with erroneous results. Consequently, it is necessary to run these applications on highly available and reliable systems, requiring strategies capable of providing detection, protection and recovery against faults. In the next years it is planned to reach Exa-scale, in which there will be supercomputers with millions of processing cores, capable of performing on the order of 1018 operations per second. This is a great window of opportunity for HPC applications, but it also increases the risk that they will not complete their executions. Recent studies show that, as systems continue to include more processors, the Mean Time Between Errors decreases, resulting in higher failure rates and increased risk of corrupted results; large parallel applications are expected to deal with errors that occur every few minutes, requiring external help to progress efficiently. Silent Data Corruptions are the most dangerous errors that can occur, since they can generate incorrect results in programs that appear to execute correctly. Scientific applications and large-scale simulations are the most affected, making silent error handling the main challenge towards resilience in HPC. In message passing applications, a silent error, affecting a single task, can produce a pattern of corruption that spreads to all communicating processes; in the worst case scenario, the erroneous final results cannot be detected at the end of the execution and will be taken as correct. Since scientific applications have execution times of the order of hours or even days, it is essential to find strategies that allow applications to reach correct solutions in a bounded time, despite the underlying failures. These strategies also prevent energy consumption from skyrocketing, since if they are not used, the executions should be launched again from the beginning. However, the most popular parallel programming models used in supercomputers lack support for fault tolerance.

Impact of Intercalation Doping on the Conductivity of Multi-Layer Graphene Nanoribbon (MLGNR) in On-Chip Interconnects

2020 ◽  
Vol 29 (12) ◽  
pp. 2050185 ◽  
Author(s):  
Himanshu Sharma ◽  
Karmjit Singh Sandha
Keyword(s):  
Integrated Circuit ◽  
Fermi Energy ◽  
Large Scale ◽  
Graphene Nanoribbons ◽  
Layer Graphene ◽  
Parasitic Parameters ◽  
On Chip ◽  
Power Delay Product ◽  
Technology Nodes ◽  
The Impact

Graphene nanoribbons are considered potentially suitable and have exhibited excellent results in on-chip interconnects. In order to evaluate the different circuit impedance parameters of multi-layer graphene nanoribbons (MLGNRs), an electrical equivalent single conductor (ESC) along with an analytical model is proposed. On the basis of an electrical model, the impact of intercalation doping on the performance of MLGNRs at 32, 22, and 16[Formula: see text]nm technology nodes is discussed in this paper. Moreover, it is also discussed that the increase in intercalation doping increases the Fermi energy of the layers of the MLGNR, which increases its overall conductivity. The fact that the variation in the Fermi energy will have a considerable impact on the parasitic parameters of the MLGNR interconnect at three different technology nodes (32, 22, and 16[Formula: see text]nm) for variable global lengths (500–2000[Formula: see text][Formula: see text]m) is also analyzed. To estimate and compare the performance in terms of delay and power delay product (PDP) of MLGNRs, the simulation program with integrated circuit emphasis (SPICE) simulation tool is used. The results also show that the increase in the Fermi energy improves the performance of MLGNRs in terms of delay and PDP at three different technology nodes. Furthermore, a comparative analysis of all three technology nodes is performed with the copper interconnect, and it is revealed that the MLGNR interconnect is considered to be a prominent material for the next-generation on-chip very-large-scale integration interconnects.

scholarly journals LEVERAGING MATURITY ASSESSMENT TO CHOOSE THE RIGHT APPLICATIONS FOR SMART CITIES: TURKEY’S APPROACH

2020 ◽  
Vol XLIV-4/W3-2020 ◽  
pp. 137-142
Author(s):  
H. Bayraktar ◽  
D. Y. Bayar ◽  
B. Kara ◽  
G. Bilgin
Keyword(s):  
Environmental Sustainability ◽  
Smart City ◽  
Large Scale ◽  
Smart Cities ◽  
Implementation Process ◽  
Environmental Benefits ◽  
Assessment Model ◽  
Maturity Assessment ◽  
The Right ◽  
The Impact

Abstract. Cities are facing numerous challenges because of the unprecedented growth of population all over the world. In this context, smart city stands out as a viable option to improve quality of life. Smart city, with its ability to transform the information into economic, social and environmental benefits, offers acquisitions in the fields of sustainable development, competitiveness and environmental sustainability. However, the cost of implementing and maintaining smart city applications on a large scale reveals the necessity to choose the right smart city application at the beginning of smart city transformation. In order to determine which smart city application should be used in smart city domain, the current situation and needs of the city should be analysed effectively. Maturity assessment can be used as a tool to understand the existing conditions of a city. In this study, Turkey's smart city approach will be addressed and Smart City Maturity Assessment Model of Turkey will be introduced with the preparation and implementation process. Consequently, the impact of the Smart City Maturity Assessment Model on selection of smart city applications will be discussed with the result of maturity assessment which is implemented on 4 cities of Turkey.

A Flexible Fault Injection Platform for the Analysis of the Symptoms of Soft Errors in FPGA Soft Processors

2017 ◽  
Vol 26 (08) ◽  
pp. 1740009
Author(s):  
Aitzan Sari ◽  
Mihalis Psarakis
Keyword(s):  
Error Detection ◽  
Fault Tolerant ◽  
Fault Injection ◽  
Low Cost ◽  
Soft Errors ◽  
Soft Error ◽  
Detection Scheme ◽  
Detection Techniques ◽  
Error Sensitivity ◽  
Depth Analysis

Due to the high vulnerability of SRAM-based FPGAs in single-event upsets (SEUs), effective fault tolerant soft processor architectures must be considered when we use FPGAs to build embedded systems for critical applications. In the past, the detection of symptoms of soft errors in the behavior of microprocessors has been used for the implementation of low-budget error detection techniques, instead of costly hardware redundancy techniques. To enable the development of such low-cost error detection techniques for FPGA soft processors, we propose an in-depth analysis of the symptoms of SEUs in the FPGA configuration memory. To this end, we present a flexible fault injection platform based on an open-source CAD framework (RapidSmith) for the soft error sensitivity analysis of soft processors in Xilinx SRAM-based FPGAs. Our platform supports the estimation of soft error sensitivity per configuration bit/frame, processor component and benchmark. The fault injection is performed on-chip by a dedicated microcontroller which also monitors processor behavior to identify specific symptoms as consequences of soft errors. The performed analysis showed that these symptoms can be used to build an efficient, low-cost error detection scheme. The proposed platform is demonstrated through an extensive fault injection campaign in the Leon3 soft processor.

Impact of COVID-19 on Nuclear Medicine in Germany, Austria and Switzerland: An International Survey in April 2020

2020 ◽  
Vol 59 (04) ◽  
pp. 294-299 ◽  
Author(s):  
Lutz S. Freudenberg ◽  
Ulf Dittmer ◽  
Ken Herrmann
Keyword(s):  
Nuclear Medicine ◽  
Health Systems ◽  
Personal Protective Equipment ◽  
Large Scale ◽  
Diagnostic Procedures ◽  
Protective Equipment ◽  
Current Crisis ◽  
Web Based ◽  
Public Versus Private ◽  
The Impact

Abstract Introduction Preparations of health systems to accommodate large number of severely ill COVID-19 patients in March/April 2020 has a significant impact on nuclear medicine departments. Materials and Methods A web-based questionnaire was designed to differentiate the impact of the pandemic on inpatient and outpatient nuclear medicine operations and on public versus private health systems, respectively. Questions were addressing the following issues: impact on nuclear medicine diagnostics and therapy, use of recommendations, personal protective equipment, and organizational adaptations. The survey was available for 6 days and closed on April 20, 2020. Results 113 complete responses were recorded. Nearly all participants (97 %) report a decline of nuclear medicine diagnostic procedures. The mean reduction in the last three weeks for PET/CT, scintigraphies of bone, myocardium, lung thyroid, sentinel lymph-node are –14.4 %, –47.2 %, –47.5 %, –40.7 %, –58.4 %, and –25.2 % respectively. Furthermore, 76 % of the participants report a reduction in therapies especially for benign thyroid disease (-41.8 %) and radiosynoviorthesis (–53.8 %) while tumor therapies remained mainly stable. 48 % of the participants report a shortage of personal protective equipment. Conclusions Nuclear medicine services are notably reduced 3 weeks after the SARS-CoV-2 pandemic reached Germany, Austria and Switzerland on a large scale. We must be aware that the current crisis will also have a significant economic impact on the healthcare system. As the survey cannot adapt to daily dynamic changes in priorities, it serves as a first snapshot requiring follow-up studies and comparisons with other countries and regions.

HOME VISITS DURING THE FIRST MONTH OF DELIVERY FOR RECENTLY DELIVERED WOMEN IN UTTAR PRADESH, INDIA

2020 ◽  
Vol 6 (5) ◽  
pp. 1183-1189
Author(s):  
Dr. Tridibesh Tripathy ◽  
Dr. Umakant Prusty ◽  
Dr. Chintamani Nayak ◽  
Dr. Rakesh Dwivedi ◽  
Dr. Mohini Gautam
Keyword(s):  
Large Scale ◽  
National Level ◽  
Uttar Pradesh ◽  
Life Time ◽  
Structured Interview ◽  
The Other ◽  
Registration System ◽  
Action Group ◽  
Current Article ◽  
The Impact

The current article of Uttar Pradesh (UP) is about the ASHAs who are the daughters-in-law of a family that resides in the same community that they serve as the grassroots health worker since 2005 when the NRHM was introduced in the Empowered Action Group (EAG) states. UP is one such Empowered Action Group (EAG) state. The current study explores the actual responses of Recently Delivered Women (RDW) on their visits during the first month of their recent delivery. From the catchment area of each of the 250 ASHAs, two RDWs were selected who had a child in the age group of 3 to 6 months during the survey. The response profiles of the RDWs on the post- delivery first month visits are dwelled upon to evolve a picture representing the entire state of UP. The relevance of the study assumes significance as detailed data on the modalities of postnatal visits are available but not exclusively for the first month period of their recent delivery. The details of the post-delivery first month period related visits are not available even in large scale surveys like National Family Health Survey 4 done in 2015-16. The current study gives an insight in to these visits with a five-point approach i.e. type of personnel doing the visit, frequency of the visits, visits done in a particular week from among those four weeks separately for the three visits separately. The current study is basically regarding the summary of this Penta approach for the post- delivery one-month period.     The first month period after each delivery deals with 70% of the time of the postnatal period & the entire neonatal period. Therefore, it does impact the Maternal Mortality Rate & Ratio (MMR) & the Neonatal Mortality Rates (NMR) in India and especially in UP through the unsafe Maternal & Neonatal practices in the first month period after delivery. The current MM Rate of UP is 20.1 & MM Ratio is 216 whereas the MM ratio is 122 in India (SRS, 2019). The Sample Registration System (SRS) report also mentions that the Life Time Risk (LTR) of a woman in pregnancy is 0.7% which is the highest in the nation (SRS, 2019). This means it is very risky to give birth in UP in comparison to other regions in the country (SRS, 2019). This risk is at the peak in the first month period after each delivery. Similarly, the current NMR in India is 23 per 1000 livebirths (UNIGME,2018). As NMR data is not available separately for states, the national level data also hold good for the states and that’s how for the state of UP as well. These mortalities are the impact indicators and such indicators can be reduced through long drawn processes that includes effective and timely visits to RDWs especially in the first month period after delivery. This would help in making their post-natal & neonatal stage safe. This is the area of post-delivery first month visit profile detailing that the current article helps in popping out in relation to the recent delivery of the respondents.   A total of four districts of Uttar Pradesh were selected purposively for the study and the data collection was conducted in the villages of the respective districts with the help of a pre-tested structured interview schedule with both close-ended and open-ended questions.  The current article deals with five close ended questions with options, two for the type of personnel & frequency while the other three are for each of the three visits in the first month after the recent delivery of respondents. In addition, in-depth interviews were also conducted amongst the RDWs and a total 500 respondents had participated in the study.   Among the districts related to this article, the results showed that ASHA was the type of personnel who did the majority of visits in all the four districts. On the other hand, 25-40% of RDWs in all the 4 districts replied that they did not receive any visit within the first month of their recent delivery. Regarding frequency, most of the RDWs in all the 4 districts received 1-2 times visits by ASHAs.   Regarding the first visit, it was found that the ASHAs of Barabanki and Gonda visited less percentage of RDWs in the first week after delivery. Similarly, the second visit revealed that about 1.2% RDWs in Banda district could not recall about the visit. Further on the second visit, the RDWs responded that most of them in 3 districts except Gonda district did receive the second postnatal visit in 7-15 days after their recent delivery. Less than half of RDWs in Barabanki district & just more than half of RDWs in Gonda district received the third visit in 15-21 days period after delivery. For the same period, the majority of RDWs in the rest two districts responded that they had been entertained through a home visit.

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