Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels

2009 ◽  
Author(s):  
G. Paci ◽  
D. Bertozzi ◽  
L. Benini
Keyword(s):  
Supply Voltage ◽  
Communication Channels ◽  
Variability Compensation ◽  
On Chip ◽  
Full Swing ◽  
Body Bias

A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation

2014 ◽  
Vol E97.A (3) ◽  
pp. 734-740 ◽  
Author(s):  
Norihiro KAMAE ◽  
Akira TSUCHIYA ◽  
Hidetoshi ONODERA
Keyword(s):  
Supply Voltage ◽  
Variability Compensation ◽  
Low Supply Voltage ◽  
Body Bias

Variability compensation for full-swing against low-swing on-chip communication

2011 ◽  
Vol 5 (5) ◽  
pp. 355
Author(s):  
G. Paci ◽  
D. Bertozzi ◽  
L. Benini
Keyword(s):  
Variability Compensation ◽  
On Chip ◽  
Full Swing

COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS

2014 ◽  
Vol 23 (08) ◽  
pp. 1450108 ◽  
Author(s):  
VANDANA NIRANJAN ◽  
ASHWANI KUMAR ◽  
SHAIL BALA JAIN
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Signal Frequency ◽  
Output Impedance ◽  
Self Cascode ◽  
Intrinsic Gain ◽  
Body Bias

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

LOOKUP TABLE-BASED ADAPTIVE BODY BIASING OF MULTIPLE MACROS FOR PROCESS VARIATION COMPENSATION AND LOW LEAKAGE

2010 ◽  
Vol 19 (07) ◽  
pp. 1449-1464 ◽  
Author(s):  
BYUNGHEE CHOI ◽  
YOUNGSOO SHIN
Keyword(s):  
Supply Voltage ◽  
Process Variation ◽  
Power Saving ◽  
Lookup Table ◽  
Low Leakage ◽  
Fine Grain ◽  
Body Biasing ◽  
Block Level ◽  
Adaptive Body Bias ◽  
Body Bias

A reduced supply voltage must be accompanied by a reduced threshold voltage, which makes this approach to power saving susceptible to process variation in transistor parameters, as well as resulting in increased subthreshold leakage. While adaptive body biasing is efficient for both compensating process variation and suppressing leakage current, it suffers from a large overhead of control circuit. Most body biasing circuits target an entire chip, which causes excessive leakage of some blocks and misses the chance of fine grain control. We propose a new adaptive body biasing scheme, based on a lookup table for independent control of multiple functional blocks on a chip, which controls leakage and also compensates for process variation at the block level. An adaptive body bias is applied to blocks in active mode and a large reverse body bias is applied to blocks in standby mode. This is achieved by a central body bias controller, which has a low overhead in terms of area, delay, and power consumption. The problem of optimizing the required set of bias voltages is formulated and solved. A design methodology for semicustom design using standard-cell elements is developed and verified with benchmark circuits.

A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation

2014 ◽  
Author(s):  
Norihiro Kamae ◽  
A. K. M. Mahfuzul Islam ◽  
Akira Tsuchiya ◽  
Hidetoshi Onodera
Keyword(s):  
Threshold Voltage ◽  
Variability Compensation ◽  
Body Bias

An analog on-chip adaptive body bias calibration for reducing mismatches in transistor pairs

2008 ◽  
Author(s):  
P. B. Bacinschi ◽  
T. Murgan ◽  
K. Koch ◽  
M. Glesner
Keyword(s):  
Adaptive Body Bias ◽  
On Chip ◽  
Body Bias

A ΣΔ MODULATOR USING GAIN-BOOST CLASS-C INVERTER FOR AUDIO APPLICATIONS

2013 ◽  
Vol 22 (10) ◽  
pp. 1340024
Author(s):  
HAO LUO ◽  
YAN HAN ◽  
RAY C. C. CHEUNG ◽  
TIANLIN CAO ◽  
XIAOPENG LIU ◽  
...  
Keyword(s):  
High Resolution ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Process ◽  
Signal To Noise ◽  
Dc Gain ◽  
Micro Power ◽  
Class C ◽  
On Chip ◽  
Σδ Modulator

This paper provides an audio 2-1 cascaded ΣΔ modulator using a novel gain-boost class-C inverter. The gain-boost class-C inverter behaves as a subthreshold amplifier. By introducing a gain-boost module, the inverter DC-gain is increased from 48 dB to 67 dB. The gain-boost class-C inverter consumes 57 μW at 1.2-V supply, where the gain-boost module consumes only 3 μW. In addition, an on-chip body bias technique is introduced to compensate the process and supply voltage variations of the class-C inverter. The proposed inverter-based ΣΔ modulator chip is implemented in 0.13-μm CMOS process, and achieves 86-dB peak-signal to noise and distortion ratio (SNDR) and 90-dB dynamic range (DR) over 22.05-KHz bandwidth at 1.2-V supply consuming 360 μW, which demonstrates that the gain-boost class-C inverter is particularly suitable for micro-power high-resolution applications.

An Adaptively Biased Capacitor-Less Low Dropout Regulator with Improved Transient Performance

2017 ◽  
Vol 26 (10) ◽  
pp. 1750146
Author(s):  
Suresh Alapati ◽  
Sreehari Rao Patri ◽  
K. S. R. Krishna Prasad
Keyword(s):  
Supply Voltage ◽  
Cmos Process ◽  
Transient Performance ◽  
Linear Regulator ◽  
Current Change ◽  
Load Regulation ◽  
Low Dropout Regulator ◽  
On Chip ◽  
Fast Rise ◽  
Fixed Bias

A novel fully on-chip low dropout (LDO) linear regulator with a supply voltage of 1.6[Formula: see text]V, dropout voltage of 200[Formula: see text]mV and a quiescent current of 64.4[Formula: see text][Formula: see text]A is presented in this paper. The slew rate limitations of conventional low dropout regulator (LDR) employing folded cascode structure are overcome by fixed bias LDR (FB LDR) with the usage of recycled transistors of conventional LDR. The FB LDR with its limited input common mode range limits the transient response. The adaptive bias LDR (AB LDR) overcomes these limitations of FB LDR and further enhances the transient performance. However, fast rise and fall time demands of advanced digital technology demand the regulator to respond to corresponding fast load changes. These challenges are addressed by an additional fast reacting path. An undershoot of 89.95[Formula: see text]mV for a load current changes from 0[Formula: see text]mA to 100[Formula: see text]mA and an overshoot of 150.1[Formula: see text]mV for a current change of 100–0[Formula: see text]mA is observed for the adaptive bias transient enhanced LDR. The load regulation of 20.6[Formula: see text][Formula: see text]V/mA and power supply rejection (PSR) of [Formula: see text]47.8[Formula: see text]dB@ 10[Formula: see text]kHz is achieved due to the improved closed loop gain and bandwidth of LDR. The standard 180[Formula: see text]nm UMC CMOS process is employed.

On-Chip Supply Voltage Conversion System and Its Application to a 4Mb DRAM

1986 ◽  
Author(s):  
Yohji WATANABE ◽  
Shigeyoshi WATANABE ◽  
Takashi OHSAWA ◽  
Tohru FURUYAMA ◽  
Kazunori OHUCHI
Keyword(s):  
Supply Voltage ◽  
Conversion System ◽  
On Chip ◽  
Voltage Conversion
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