AbstractWe fabricated and studied the performance of Schottky-Barrier Si nanowire FETs (SiNW FET) by using Vapor-liquid-solid (VLS) grown Au-catalyzed SiNWs (20 nm). These devices were formed on various gate dielectrics (HfO2 or Al2O3) with different metal Source and Drain (S/D) regions (Pd, Ni). P-type behavior was observed and high Ion/Ioff ratio (~105) was achieved from undoped SiNW FETs. Besides, no ambipolar transportation was observed in our devices performance. This is possibly due to the small schottky barrier height for hole carriers at Source sides formed by high work-function metal. Furthermore, low subthreshold slope as 68mV/decade was obtained from SiNW FETs integrated with Ni S/D and Al2O3 High-¦gate dielectric.
Three-dimensional Modeling of Gate Leakage in Si Nanowire Transistors