Development of the wafer level compressive-flow underfill process and its required materials

2003 ◽  
Author(s):  
S.H. Shi ◽  
T. Yamashita ◽  
C.P. Wong
Keyword(s):  
Wafer Level ◽  
Compressive Flow

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging

Silicon Migration Seal Wafer-Level Vacuum Encapsulation

2020 ◽  
Vol 140 (7) ◽  
pp. 165-169
Author(s):  
Yukio Suzuki ◽  
Dupuit Victor ◽  
Toshiya Kojima ◽  
Yoshiaki Kanamori ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level

Development of Wafer Level Chip Size Packaging Process and its Application to the CMOS Image Sensor Module for Medical Device

2017 ◽  
Vol 137 (2) ◽  
pp. 48-58
Author(s):  
Noriyuki Fujimori ◽  
Takatoshi Igarashi ◽  
Takahiro Shimohata ◽  
Takuro Suyama ◽  
Kazuhiro Yoshida ◽  
...  
Keyword(s):  
Medical Device ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Wafer Level ◽  
Packaging Process ◽  
Sensor Module ◽  
Chip Size

Low Temperature Al-Al Thermo-compression Bonding with Sn Oxidation Protect Layer for Wafer-level Hermetic Sealing

2016 ◽  
Vol 136 (6) ◽  
pp. 237-243 ◽  
Author(s):  
Shiro Satoh ◽  
Hideyuki Fukushi ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Low Temperature ◽  
Wafer Level ◽  
Hermetic Sealing

3D IC/Stacked Device Fault Isolation Using 3D Magnetic Field Imaging

2014 ◽  
Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Fault Isolation ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Current Location ◽  
Geometrical Information ◽  
Magnetic Field Imaging ◽  
Silicon Vias ◽  
Non Destructive ◽  
Field Imaging

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

Analysis of FSRAM Single Bit Failures Due to Unique Dislocations

1998 ◽  
Author(s):  
Phil Schani ◽  
S. Subramanian ◽  
Vince Soorholtz ◽  
Pat Liston ◽  
Jamey Moss ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Temperature Sensitive ◽  
Wafer Level ◽  
Top Down ◽  
Access Memory ◽  
Transmission Electron ◽  
Contact Processing

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.

Characterization of Unfilled Tungsten Plugs on a 0.35μm CMOS Multilevel Metallization Process

1996 ◽  
Author(s):  
H. Sur ◽  
S. Bothra ◽  
Y. Strunk ◽  
J. Hahn
Keyword(s):  
Process Development ◽  
Process Integration ◽  
Wafer Level ◽  
Electrical Failure ◽  
Analysis Techniques ◽  
Integration Approach ◽  
Intermetal Dielectric ◽  
Metallization Process ◽  
Section Analysis

Abstract An investigation into metallization/interconnect failures during the process development phase of an advanced 0.35μm CMOS ASIC process is presented. The corresponding electrical failure signature was electrical shorting on SRAM test arrays and subsequently functional/Iddq failures on product-like test vehicles. Advanced wafer-level failure analysis techniques and equipment were used to isolate and identify the leakage source as shorting of metal lines due to tungsten (W) residue which was originating from unfilled vias. Further cross-section analysis revealed that the failing vias were all exposed to the intermetal dielectric spin-on glass (SOG) material used for filling the narrow spaces between metal lines. The outgassing of the SOG in the exposed regions of the via prior to and during the tungsten plug deposition is believed to be the cause of the unfilled vias. This analysis facilitated further process development in eliminating the failure mechanism and since then no failures of this nature have been observed. The process integration approach used to eliminate the failure is discussed.

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