Silicon Migration Seal Wafer-Level Vacuum Encapsulation

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

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Analysis of FSRAM Single Bit Failures Due to Unique Dislocations

ISTFA 1998: Conference Proceedings from the 24th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa1998p0373 ◽

1998 ◽

Author(s):

Phil Schani ◽

S. Subramanian ◽

Vince Soorholtz ◽

Pat Liston ◽

Jamey Moss ◽

...

Keyword(s):

Electron Microscopy ◽

Random Access ◽

Random Access Memory ◽

Static Random Access Memory ◽

Temperature Sensitive ◽

Wafer Level ◽

Top Down ◽

Access Memory ◽

Transmission Electron ◽

Contact Processing

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.

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Characterization of Unfilled Tungsten Plugs on a 0.35μm CMOS Multilevel Metallization Process

ISTFA 1996: Conference Proceedings from the 22nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa1996p0141 ◽

1996 ◽

Author(s):

H. Sur ◽

S. Bothra ◽

Y. Strunk ◽

J. Hahn

Keyword(s):

Process Development ◽

Process Integration ◽

Wafer Level ◽

Electrical Failure ◽

Analysis Techniques ◽

Integration Approach ◽

Intermetal Dielectric ◽

Metallization Process ◽

Section Analysis

Abstract An investigation into metallization/interconnect failures during the process development phase of an advanced 0.35μm CMOS ASIC process is presented. The corresponding electrical failure signature was electrical shorting on SRAM test arrays and subsequently functional/Iddq failures on product-like test vehicles. Advanced wafer-level failure analysis techniques and equipment were used to isolate and identify the leakage source as shorting of metal lines due to tungsten (W) residue which was originating from unfilled vias. Further cross-section analysis revealed that the failing vias were all exposed to the intermetal dielectric spin-on glass (SOG) material used for filling the narrow spaces between metal lines. The outgassing of the SOG in the exposed regions of the via prior to and during the tungsten plug deposition is believed to be the cause of the unfilled vias. This analysis facilitated further process development in eliminating the failure mechanism and since then no failures of this nature have been observed. The process integration approach used to eliminate the failure is discussed.

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WLCSP Laminate Removal Using NIR Laser

10.31399/asm.cp.istfa2018p0486 ◽

2018 ◽

Author(s):

Chun Haur Khoo

Keyword(s):

Near Infrared ◽

Laser Energy ◽

Photon Emission ◽

Mechanical Damage ◽

Consumer Products ◽

Fault Isolation ◽

Wafer Level ◽

Isolation Technique ◽

Laminate Layer ◽

Nir Laser

Abstract Driven by the cost reduction and miniaturization, Wafer Level Chip Scale Packaging (WLCSP) has experienced significant growth mainly driven by mobile consumer products. Depending on the customers or manufacturing needs, the bare silicon backside of the WLCSP may be covered with a backside laminate layer. In the failure analysis lab, in order to perform the die level backside fault isolation technique using Photon Emission Microscope (PEM) or Laser Signal Injection Microscope (LSIM), the backside laminate layer needs to be removed. Most of the time, this is done using the mechanical polishing method. This paper outlines the backside laminate removal method of WLCSP using a near infrared (NIR) laser that produces laser energy in the 1,064 nm range. This method significantly reduces the sample preparation time and also reduces the risk of mechanical damage as there is no application of mechanical force. This is an effective method for WLCSP mounted on a PCB board.

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Sample Preparation Challenges In WLCSP Epoxy Underfill Coating Removal

ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2012p0471 ◽

2012 ◽

Author(s):

Jason H. Lagar ◽

Rudolf A. Sia

Keyword(s):

Sample Preparation ◽

Failure Analysis ◽

Vital Role ◽

Fault Isolation ◽

Wafer Level ◽

Chip Scale Package ◽

Coating Removal ◽

Customer Returns ◽

Preparation Techniques ◽

Mechanical Defect

Abstract Most Wafer Level Chip Scale Package (WLCSP) units returned by customers for failure analysis are mounted on PCB modules with an epoxy underfill coating. The biggest challenge in failure analysis is the sample preparation to remove the WLCSP device from the PCB without inducing any mechanical defect. This includes the removal of the underfill material to enable further electrical verification and fault isolation analysis. This paper discusses the evaluations conducted in establishing the WLCSP demounting process and removal of the epoxy underfill coating. Combinations of different sample preparation techniques and physical failure analysis steps were evaluated. The established process enabled the electrical verification, fault isolation and further destructive analysis of WLCSP customer returns mounted on PCB and with an epoxy underfill coating material. This paper will also showcase some actual full failure analysis of WLCSP customer returns where the established process played a vital role in finding the failure mechanism.

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A New Method of Wafer Level Plan View TEM Sample Preparation by DualBeam

ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2008p0168 ◽

2008 ◽

Author(s):

Hyoung H. Kang ◽

Michael A. Gribelyuk ◽

Oliver D. Patterson ◽

Steven B. Herschbein ◽

Corey Senowitz

Keyword(s):

Sample Preparation ◽

Ex Situ ◽

Wafer Level ◽

Cross Sectional ◽

Plan View ◽

Manufacturing Line ◽

Transmission Electron ◽

Thin Lamella ◽

Preparation Techniques

Abstract Cross-sectional style transmission electron microscopy (TEM) sample preparation techniques by DualBeam (SEM/FIB) systems are widely used in both laboratory and manufacturing lines with either in-situ or ex-situ lift out methods. By contrast, however, the plan view TEM sample has only been prepared in the laboratory environment, and only after breaking the wafer. This paper introduces a novel methodology for in-line, plan view TEM sample preparation at the 300mm wafer level that does not require breaking the wafer. It also presents the benefit of the technique on electrically short defects. The methodology of thin lamella TEM sample preparation for plan view work in two different tool configurations is also presented. The detailed procedure of thin lamella sample preparation is also described. In-line, full wafer plan view (S)TEM provides a quick turn around solution for defect analysis in the manufacturing line.

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