Wafer level warpage characterization for backside manufacturing processes of TSV interposers

Author(s):  
Feng Jiang ◽  
Qibin Wang ◽  
Kai Xue ◽  
Xiangmeng Jing ◽  
Daquan Yu ◽  
...  
2008 ◽  
Vol 1139 ◽  
Author(s):  
Viorel Dragoi ◽  
Gerald Mittendorfer ◽  
Franz Murauer ◽  
Erkan Cakmak ◽  
Eric Pabo

AbstractMetal layers can be used as bonding layers at wafer-level in MEMS manufacturing processes for device assembly as well as just for electrical integration of different levels. One has to distinguish between two main types of processes: metal diffusion bonding and bonding with formation of an interface eutectic alloy layer or an intermetallic compound. The different process principles determine also the applications area for each. From electrical interconnections to wafer-level packaging (with emphasis on vacuum packaging) metal wafer bonding is a very important technology in MEMS manufacturing processes.


2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001137-001176
Author(s):  
Jeff Perkins

If LED lighting is to fulfill the promise it holds across all lighting segments, costs need to drop significantly and production volumes will need to double several times over in the coming years. To achieve both, cost improvements must happen at every level of manufacturing and manufacturing processes must evolve. When talking about LED device costs today, packaging holds the greatest cost saving opportunities. As with many semiconductor devices and for LED devices in particular, wafer level packaging will be a key cost saving move for the future. Much needs to be done and much is being done - this talk will take a look at the full spectrum of developments to bring LED into mainstream lighting applications.


TAPPI Journal ◽  
2018 ◽  
Vol 17 (08) ◽  
pp. 437-443
Author(s):  
Lebo Xu ◽  
Jeremy Meyers ◽  
Peter Hart

Coffee edge-wicking testing was conducted on two groups of highly-sized paperboard manufactured at two mills with similar manufacturing processes, but with vastly different local fiber sources. Although the Hercules size test (HST) indicated similar internal size levels between the two types of board, the edge-wicking behavior was noticeably different. Analysis of fiber structure revealed that the board with more edge-wicking had fibers with thicker fiber walls, which kept the fiber lumen more open after pressing and drying on a paper machine. It was demonstrated that liquid penetration through voids between fibers in highly-sized paperboard was limited, because the fiber surface was well protected by the presence of sufficient sizing agent. Nevertheless, freshly exposed fiber walls and lumens at the cut edge of the sheet were not protected by sizing material, which facilitated edge-wicking. The correlation between fiber structure and edge-wicking behavior was highlighted in this work to inspire development of novel sizing strategies that protect the freshly cut edge of the sheet from edge-wicking.


2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka

2020 ◽  
Vol 140 (7) ◽  
pp. 165-169
Author(s):  
Yukio Suzuki ◽  
Dupuit Victor ◽  
Toshiya Kojima ◽  
Yoshiaki Kanamori ◽  
Shuji Tanaka
Keyword(s):  

2017 ◽  
Vol 137 (2) ◽  
pp. 48-58
Author(s):  
Noriyuki Fujimori ◽  
Takatoshi Igarashi ◽  
Takahiro Shimohata ◽  
Takuro Suyama ◽  
Kazuhiro Yoshida ◽  
...  

2016 ◽  
Vol 136 (6) ◽  
pp. 237-243 ◽  
Author(s):  
Shiro Satoh ◽  
Hideyuki Fukushi ◽  
Masayoshi Esashi ◽  
Shuji Tanaka

Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.


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