Analysis of Interface Trap Charges of Double Gate Junctionless Nanowire Transistor (DG-JNT)for Digital Circuit Applications

2018 IEEE Electron Devices Kolkata Conference (EDKCON) ◽

10.1109/edkcon.2018.8770427 ◽

2018 ◽

Author(s):

Neha Garg ◽

Yogesh Pratap ◽

Mridula Gupta ◽

Sneha Kabra

Keyword(s):

Digital Circuit ◽

Interface Trap ◽

Double Gate ◽

Nanowire Transistor ◽

Junctionless Nanowire Transistor ◽

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Analytical drain current model to study the impact of interface trap charges on device performance of Double Gate Ge Ferroelectric FET (DGGeFeFET)

2018 Conference on Emerging Devices and Smart Systems (ICEDSS) ◽

10.1109/icedss.2018.8544314 ◽

2018 ◽

Author(s):

Monika Bansal ◽

Harsupreet Kaur

Keyword(s):

Current Model ◽

Drain Current ◽

Interface Trap ◽

Device Performance ◽

Double Gate ◽

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3D Double-Gate Junctionless Nanowire Transistor-Based Pass Transistor Logic Circuits for Digital Applications

IETE Journal of Research ◽

10.1080/03772063.2019.1649203 ◽

2019 ◽

pp. 1-8

Author(s):

Achinta Baidya ◽

Trupti R. Lenka ◽

Srimanta Baishya

Keyword(s):

Logic Circuits ◽

Double Gate ◽

Nanowire Transistor ◽

Pass Transistor ◽

Pass Transistor Logic ◽

Junctionless Nanowire Transistor

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An analytical model for long channel Double Gate Ge Ferroelectric FET (DGGeFeFET) to study the impact of interface trap charges

2017 International Conference On Smart Technologies For Smart Nation (SmartTechCon) ◽

10.1109/smarttechcon.2017.8358506 ◽

2017 ◽

Author(s):

Monika Bansal ◽

Harsupreet Kaur

Keyword(s):

Analytical Model ◽

Interface Trap ◽

Double Gate ◽

Long Channel ◽

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Impact of different localized trap charge profiles on the short channel double gate junctionless nanowire transistor based inverter and Ring Oscillator circuit

AEU - International Journal of Electronics and Communications ◽

10.1016/j.aeue.2019.06.014 ◽

2019 ◽

Vol 108 ◽

pp. 251-261 ◽

Author(s):

Neha Garg ◽

Yogesh Pratap ◽

Mridula Gupta ◽

Sneha Kabra

Keyword(s):

Ring Oscillator ◽

Double Gate ◽

Short Channel ◽

Trap Charge ◽

Oscillator Circuit ◽

Nanowire Transistor ◽

Junctionless Nanowire Transistor

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Impact of Interface Trap Charges on Analog/RF and Linearity Performances of Dual-Material Gate-Oxide-Stack Double-Gate TFET

IEEE Transactions on Device and Materials Reliability ◽

10.1109/tdmr.2020.2984669 ◽

2020 ◽

Vol 20 (2) ◽

pp. 404-412

Author(s):

Km. Sucheta Singh ◽

Satyendra Kumar ◽

Kaushal Nigam

Keyword(s):

Interface Trap ◽

Double Gate ◽

Dual Material ◽

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Impact of negative capacitance effect on Germanium Double Gate pFET for enhanced immunity to interface trap charges

Superlattices and Microstructures ◽

10.1016/j.spmi.2018.03.001 ◽

2018 ◽

Vol 117 ◽

pp. 189-199 ◽

Author(s):

Monika Bansal ◽

Harsupreet Kaur

Keyword(s):

Interface Trap ◽

Negative Capacitance ◽

Double Gate ◽

Capacitance Effect ◽

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Mixed-mode simulation and analysis of 3D double gate junctionless nanowire transistor for CMOS circuit applications

Superlattices and Microstructures ◽

10.1016/j.spmi.2016.08.028 ◽

2016 ◽

Vol 100 ◽

pp. 14-23 ◽

Author(s):

Achinta Baidya ◽

Trupti Ranjan Lenka ◽

Srimanta Baishya

Keyword(s):

Double Gate ◽

Cmos Circuit ◽

Nanowire Transistor ◽

Junctionless Nanowire Transistor

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Low temperature electric field dependent mobility of the current oscillation regime in silicon junctionless nanowire transistor

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) ◽

10.1109/icsict49897.2020.9278148 ◽

2020 ◽

Author(s):

Chong Yang ◽

Wei-Hua Han ◽

Jun-Dong Chen ◽

Xiao-Di Zhang ◽

Yang-Yan Guo

Keyword(s):

Low Temperature ◽

Electric Field ◽

Current Oscillation ◽

Oscillation Regime ◽

Nanowire Transistor ◽

Field Dependent ◽

Junctionless Nanowire Transistor

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A Poly‐Crystalline Silicon Nanowire Transistor with Independently Controlled Double‐Gate for Physically Unclonable Function by Multi‐States and Self‐Destruction

Advanced Electronic Materials ◽

10.1002/aelm.202000989 ◽

2021 ◽

pp. 2000989

Author(s):

Ji‐Man Yu ◽

Gyeong‐Jun Yun ◽

Moon‐Seok Kim ◽

Joon‐Kyu Han ◽

Da‐Jin Kim ◽

...

Keyword(s):

Crystalline Silicon ◽

Silicon Nanowire ◽

Double Gate ◽

Nanowire Transistor

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Junctionless Nanowire Transistor (JNT): Properties and design guidelines

Solid-State Electronics ◽

10.1016/j.sse.2011.06.004 ◽

2011 ◽

Vol 65-66 ◽

pp. 33-37 ◽

Author(s):

J.P. Colinge ◽

A. Kranti ◽

R. Yan ◽

C.W. Lee ◽

I. Ferain ◽

...

Keyword(s):

Design Guidelines ◽

Nanowire Transistor ◽

Junctionless Nanowire Transistor

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