An analytical model for long channel Double Gate Ge Ferroelectric FET (DGGeFeFET) to study the impact of interface trap charges

2017 ◽  
Author(s):  
Monika Bansal ◽  
Harsupreet Kaur
Keyword(s):  
Analytical Model ◽  
Interface Trap ◽  
Double Gate ◽  
Long Channel ◽  
The Impact ◽  
Trap Charges

scholarly journals A reliability study of Non-uniform Si TFET with dual material source: Impact of interface trap charges and temperature

2021 ◽  
Author(s):  
Jagritee Talukdar ◽  
Kavicharan Mummaneni
Keyword(s):  
Interface Trap ◽  
Small Signal ◽  
Reliability Study ◽  
Material Source ◽  
Dc Characteristics ◽  
Signal Parameters ◽  
Source Voltage ◽  
The Impact ◽  
Dual Material ◽  
Trap Charges

Abstract The article reports the extraction of DC characteristics and small signal parameters of Non-uniform Si TFET with dual material source (NUTFET-DMS) at different frequencies followed by its reliability investigation. The reliability of the device is examined by analysing: 1) the impact of the presence of interface trap charges, 2) the impact of temperature variation (200 K- 400 K). In the analysis it has been observed that in case of absence of interface trap charges the increase in frequency reduces the value of parasitic capacitances. In addition, the presence of interface trap charges lessens the value of parasitic capacitances up to a certain gate to source voltage after that it shows a reverse effect. Further, it has been perceived that the effect of change in temperature is more on device ambipolar current when interface trap charges are present, whereas the reverse is true in the case of OFF state current and different parasitic capacitances.

scholarly journals Effect of positive and negative interface trap charges on the performance of M-FinFET and its RF/linearity analysis

2021 ◽  
Author(s):  
Rinku Rani Das ◽  
Atanu Chowdhury ◽  
Apurba Chakroborty ◽  
Santanu Maity
Keyword(s):  
Semiconductor Device ◽  
Cmos Technology ◽  
The Other ◽  
Interface Trap ◽  
Trap Concentration ◽  
Device Efficiency ◽  
The Impact ◽  
First Time ◽  
Intrinsic Gain ◽  
Trap Charges

Abstract Multiple Fins structured FinFET (M-FinFET) is a promising semiconductor device for future improvisation of CMOS technology. In this paper, we investigate the impact of interface trap charges (positive and negative trap) at the HfO2/Si interface in M-FinFET for the first time. The various important DC attributes, RF/analog, and linearity metrics are studied in presence and absence of traps. Simultaneously, the various trap concentration effect on the characteristics of M-FinFET are also observed. The results show that the introduction of interface trap charges (ITC) has optimized the ON current, OFF current, and also improves sub-threshold swing (SS) characteristics as compared to no trap condition. It is observed that positive trap having trap concentration of 1012/cm2 enhances the ION ~5.14x, SS by 44.75%, and various important RF/analog parameter such as transconductance (Gm) improves by a factor 5, device efficiency by 7.4% and intrinsic gain (Av) 80.4%. On the other hand, linearity parameters like VIP2, VIP3 and 1 dB compression point show better performance in presence of positive and negative trap.

scholarly journals Assessment of Interface Trap Charges on Proposed TFET for Low Power High-frequency Application

2021 ◽  
Author(s):  
Sachin Kumar ◽  
Dharmendra Singh Yadav
Keyword(s):  
Low Power ◽  
High Frequency ◽  
Superior Performance ◽  
Interface Trap ◽  
Performance Parameters ◽  
Metal Gate ◽  
Ultra Low Power ◽  
Dual Metal ◽  
The Impact ◽  
Trap Charges

Abstract Accumulation of trap charges at the semiconductor and oxide interface is the most dominating factor and cannot be neglected as it degrades device performance and reliability. This manuscript, presents detailed investigation to analyze the impact of interface trap charges (ITCs) on the performance parameters of the proposed device i.e., heterogeneous dielectric dual metal gate step channel TFET (HD DMG SC-TFET). The comparative study is conducted with dual metal gate step channel TEFT (DMG SC-TFET). The proposed device shows improved current carrying capability, suppressed ambipolar behaviour with steeper subthreshold swing. The purpose of this study to determine the ITCs impact on DC characteristics and analog/RF electrical performance parameters of the proposed device. It further observed that the proposed device exhibit superior performance due to dielectric engineering at oxide layer. Moreover, advanced communication devices must respond linearly therefore, the impact of ITCs on linearity parameters is also studied. From this brief comparative investigation, it is observed that the proposed TFET exhibits negligible distortion in linearity parameters with little or no impact of trap charges as compared to DMG SC-TFET. Thus, proposed TFET is appropriate for ultra-low power high-frequency electronic devices.

An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

2019 ◽  
Vol 9 (4) ◽  
pp. 504-511
Author(s):  
Sikha Mishra ◽  
Urmila Bhanja ◽  
Guru Prasad Mishra
Keyword(s):  
Analytical Model ◽  
Surface Potential ◽  
Threshold Voltage ◽  
Silicon On Insulator ◽  
Junction Depth ◽  
Short Channel ◽  
Soi Mosfet ◽  
Minimum Surface ◽  
Recessed Channel ◽  
The Impact

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

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