Electrical stress characteristics of MOS capacitors with p-type poly-SiGe and poly-Si gates in the direct tunneling regime

Author(s):  
M.Y.A. Yousif ◽  
M. Willander ◽  
P. Lundgren ◽  
M. Caymax
1974 ◽  
Vol 24 (2) ◽  
pp. 649-652 ◽  
Author(s):  
M. L. Korwin-Pawlowski ◽  
E. L. Heasell
Keyword(s):  

2021 ◽  
Vol 16 (06) ◽  
pp. P06040
Author(s):  
P. Asenov ◽  
P. Assiouras ◽  
A. Boziari ◽  
K. Filippou ◽  
I. Kazas ◽  
...  

2019 ◽  
Vol 30 (11) ◽  
pp. 10302-10310
Author(s):  
Yifan Jia ◽  
Hongliang Lv ◽  
Xiaoyan Tang ◽  
Chao Han ◽  
Qingwen Song ◽  
...  

1985 ◽  
Vol 32 (6) ◽  
pp. 3911-3915 ◽  
Author(s):  
Kazumichi Suzuki ◽  
Masaharu Sakagami ◽  
Eiichi Nishimura ◽  
Kikuo Watanabe
Keyword(s):  

2018 ◽  
Vol 57 (4S) ◽  
pp. 04FR01 ◽  
Author(s):  
Tsubasa Matsumoto ◽  
Hiromitsu Kato ◽  
Toshiharu Makino ◽  
Masahiko Ogura ◽  
Daisuke Takeuchi ◽  
...  

2017 ◽  
Vol 45 ◽  
pp. 1-11
Author(s):  
Rasika Dhavse ◽  
Kumar Prashant ◽  
Chetan Dabhi ◽  
Anand Darji ◽  
R.M. Patrikar

This work applies combination of Direct Tunneling model and BSIM4 based ITAT model to explain the leakage of electrons from charged nanocrystals to p-type silicon substrate in data retention condition, for an ultra-thin tunnel oxide, low voltage programmable silicon nanocrystal based flash gate stack. Basic expressions of these models are modified to incorporate the nanocrystals related charge leakage in idle mode. The concept is supported by simulating these models and comparing them with the experimental data. Transition of electrons is considered as a result of Direct Tunneling and their trapping de-trapping via water related hydrogen traps. However, it is found that modified ITAT mechanism is the dominant one. Flat-band voltage shift profile fits accurately with the model with an extrapolated 10 years device lifetime without memory closure. 3 nm thick tunnel oxide and 100 nm sized nanocrystal fabrication with Electron Beam Lithography are main features of the devices.


2006 ◽  
Vol 527-529 ◽  
pp. 1007-1010 ◽  
Author(s):  
Daniel B. Habersat ◽  
Aivars J. Lelis ◽  
G. Lopez ◽  
J.M. McGarrity ◽  
F. Barry McLean

We have investigated the distribution of oxide traps and interface traps in 4H Silicon Carbide MOS devices. The density of interface traps, Dit, was characterized using standard C-V techniques on capacitors and charge pumping on MOSFETs. The number of oxide traps, NOT, was then calculated by measuring the flatband voltage VFB in p-type MOS capacitors. The amount that the measured flatband voltage shifts from ideal, minus the contributions due to the number of filled interface traps Nit, gives an estimate for the number of oxide charges present. We found Dit to be in the low 1011cm−2eV−1 range in midgap and approaching 1012 −1013cm−2eV−1 near the band edges. This corresponds to an Nit of roughly 2.5 ⋅1011cm−2 for a typical capacitor in flatband at room temperature. This data combined with measurements of VFB indicates the presence of roughly 1.3 ⋅1012cm−2 positive NOT charges in the oxide near the interface for our samples.


2012 ◽  
Vol 711 ◽  
pp. 228-232
Author(s):  
Elias Al Alam ◽  
Ignasi Cortés ◽  
T. Begou ◽  
Antoine Goullet ◽  
Frederique Morancho ◽  
...  

MOS SiO2/GaN structures were fabricated with different surface preparation and different PECVD processes for the dielectric thin film deposition (ECR-PECVD and ICP-PECVD in continuous and pulsed modes). On the basis of C-V curves, the surface preparation steps, involving chemical etching with BOE, UV-Ozone oxidation and oxygen plasma oxidation, were compared in terms of resulting effective charge and interface trap density. A good SiO2/GaN interface quality was achieved for N-type MOS capacitances obtained both with continuousICPPECVD and ECR-PECVD deposition of the SiO2 dielectric. However, the interface quality is greatly reduced for MOS capacitors fabricated on P-type GaN.


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