Impact of On-Chip Interconnection in a Large-Scale Memristor Crossbar Array for Neural Network Accelerator and Neuromorphic Chip

2019 ◽  
Author(s):  
Taein Shin ◽  
Kyungjune Son ◽  
Seongguk Kim ◽  
Kyungjun Cho ◽  
Shinyoung Park ◽  
...  
Keyword(s):  
Neural Network ◽  
Large Scale ◽  
Crossbar Array ◽  
On Chip ◽  
Memristor Crossbar

Wafer‐Scale 2D Hafnium Diselenide Based Memristor Crossbar Array for Energy‐Efficient Neural Network Hardware

2021 ◽  
pp. 2103376 ◽  
Author(s):  
Sifan Li ◽  
Mei‐Er Pam ◽  
Yesheng Li ◽  
Li Chen ◽  
Yu‐Chieh Chien ◽  
...  
Keyword(s):  
Neural Network ◽  
Energy Efficient ◽  
Wafer Scale ◽  
Crossbar Array ◽  
Neural Network Hardware ◽  
Memristor Crossbar

scholarly journals Scalable Implementation of Hippocampal Network on Digital Neuromorphic System towards Brain-Inspired Intelligence

2020 ◽  
Vol 10 (8) ◽  
pp. 2857
Author(s):  
Wei Sun ◽  
Jiang Wang ◽  
Nan Zhang ◽  
Shuangming Yang
Keyword(s):  
Neural Network ◽  
Large Scale ◽  
Critical Role ◽  
Future Research ◽  
Calculation Algorithm ◽  
Field Programmable ◽  
Innovative System ◽  
Hippocampal Network ◽  
Single Field ◽  
On Chip

In this paper, an expanded digital hippocampal spurt neural network (HSNN) is innovatively proposed to simulate the mammalian cognitive system and to perform the neuroregulatory dynamics that play a critical role in the cognitive processes of the brain, such as memory and learning. The real-time computation of a large-scale peak neural network can be realized by the scalable on-chip network and parallel topology. By exploring the latest research in the field of neurons and comparing with the results of this paper, it can be found that the implementation of the hippocampal neuron model using the coordinate rotation numerical calculation algorithm can significantly reduce the cost of hardware resources. In addition, the rational use of on-chip network technology can further improve the performance of the system, and even significantly improve the network scalability on a single field programmable gate array chip. The neuromodulation dynamics are considered in the proposed system, which can replicate more relevant biological dynamics. Based on the analysis of biological theory and the theory of hardware integration, it is shown that the innovative system proposed in this paper can reproduce the biological characteristics of the hippocampal network and may be applied to brain-inspired intelligent subjects. The study in this paper will have an unexpected effect on the future research of digital neuromorphic design of spike neural network and the dynamics of the hippocampal network.

Nano-Crossbar Weighted Memristor-Based Convolution Neural Network Architecture for High-Performance Artificial Intelligence Applications

2021 ◽  
Vol 21 (3) ◽  
pp. 1833-1844
Author(s):  
Kyojin Kim ◽  
Kamran Eshraghian ◽  
Hyunsoo Kang ◽  
Kyoungrok Cho
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Network Architecture ◽  
High Performance ◽  
Detection Algorithm ◽  
Cross Point ◽  
Crossbar Array ◽  
Array Architecture ◽  
Keyword Detection ◽  
Memristor Crossbar

Nano memristor crossbar arrays, which can represent analog signals with smaller silicon areas, are popularly used to describe the node weights of the neural networks. The crossbar arrays provide high computational efficiency, as they can perform additions and multiplications at the same time at a cross-point. In this study, we propose a new approach for the memristor crossbar array architecture consisting of multi-weight nano memristors on each cross-point. As the proposed architecture can represent multiple integer-valued weights, it can enhance the precision of the weight coefficients in comparison with the existing memristor-based neural networks. This study presents a Radix-11 nano memristor crossbar array with weighted memristors; it validates the operations of the circuits, which use the arrays through circuit-level simulation. With the proposed Radix-11 approach, it is possible to represent eleven integer-valued weights. In addition, this study presents a neural network designed using the proposed Radix-11 weights, as an example of high-performance AI applications. The neural network implements a speech-keyword detection algorithm, and it was designed on a TensorFlow platform. The implemented keyword detection algorithm can recognize 35 Korean words with an inferencing accuracy of 95.45%, reducing the inferencing accuracy only by 2% when compared to the 97.53% accuracy of the real-valued weight case.

scholarly journals Toward Robust Cognitive 3D Brain-Inspired Cross-Paradigm System

2021 ◽  
Vol 15 ◽  
Author(s):  
Abderazek Ben Abdallah ◽  
Khanh N. Dang
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Large Scale ◽  
Three Dimensional ◽  
Network On Chip ◽  
Spike Timing ◽  
Dimensional Structure ◽  
Spiking Neural Network ◽  
3D Ics ◽  
On Chip

Spiking Neuromorphic systems have been introduced as promising platforms for energy-efficient spiking neural network (SNNs) execution. SNNs incorporate neuronal and synaptic states in addition to the variant time scale into their computational model. Since each neuron in these networks is connected to many others, high bandwidth is required. Moreover, since the spike times are used to encode information in SNN, a precise communication latency is also needed, although SNN is tolerant to the spike delay variation in some limits when it is seen as a whole. The two-dimensional packet-switched network-on-chip was proposed as a solution to provide a scalable interconnect fabric in large-scale spike-based neural networks. The 3D-ICs have also attracted a lot of attention as a potential solution to resolve the interconnect bottleneck. Combining these two emerging technologies provides a new horizon for IC design to satisfy the high requirements of low power and small footprint in emerging AI applications. Moreover, although fault-tolerance is a natural feature of biological systems, integrating many computation and memory units into neuromorphic chips confronts the reliability issue, where a defective part can affect the overall system's performance. This paper presents the design and simulation of R-NASH-a reliable three-dimensional digital neuromorphic system geared explicitly toward the 3D-ICs biological brain's three-dimensional structure, where information in the network is represented by sparse patterns of spike timing and learning is based on the local spike-timing-dependent-plasticity rule. Our platform enables high integration density and small spike delay of spiking networks and features a scalable design. R-NASH is a design based on the Through-Silicon-Via technology, facilitating spiking neural network implementation on clustered neurons based on Network-on-Chip. We provide a memory interface with the host CPU, allowing for online training and inference of spiking neural networks. Moreover, R-NASH supports fault recovery with graceful performance degradation.

scholarly journals An Efficient Interconnection System for Neural NOC Using Fault Tolerant Routing Method

2021 ◽  
Vol 2089 (1) ◽  
pp. 012069
Author(s):  
A. Pradeep kumar ◽  
Y. Devendar Reddy ◽  
T. Srinivas Reddy ◽  
K. Jamal
Keyword(s):  
Neural Network ◽  
Large Scale ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Heavy Traffic ◽  
Data Traffic ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip ◽  
Hardware Costs

Abstract Large scale Neural Network (NN) accelerators typically have multiple processing nodes that can be implemented as a multi-core chip, and can be organized on a network of chips (noise) corresponding to neurons with heavy traffic. Portions of several NoC-based NN chip-to-chip interconnect networks are linked to further enhance overall nerve amplification capacity. Large volumes of multicast on-chip or cross-chip can further complicate the construction of a cross-link network and create a NN barrier of device capacity and resources. In this paper, this refer to inter-chip and inter-chip communication strategies known as neuron connection for NN accelerators. Interconnect for powerful fault-tolerant routing system neural NoC is implemented in this paper. This recommends crossbar arbitration placement, virtual interrupts, and path-based parallelization strategies in terms of intra-chip communications for the virtual channel routing resulting in higher NoC output at lower hardware costs. A lightweight NoC compatible chip-to-chip interconnection scheme is proposed regarding to inter-chip communication for multicast-based data traffic to enable efficient interconnection for NoC-based NN chips. Moreover, the proposed methods will be tested with four Field Programmable Gate Arrays (FPGAs) on four hard-wired deep neural network (DNN) chips. From the experimental results it can be illustrate that a high throguput can obtained effectively by the proposed interconnection network in handling thedata traffic and low DNN through advanced links.

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