Thin Wafer De-bonding for 3D-TSV Packaging of High Bandwidth Memory Devices using UV Irradiation

Author(s):  
Yongchul Shin ◽  
Kyungran Kim ◽  
Minjae Shin ◽  
Hyunjin Lee ◽  
Nung-Pyo Hong ◽  
...  
Author(s):  
S. G. Ghonge ◽  
E. Goo ◽  
R. Ramesh ◽  
R. Haakenaasen ◽  
D. K. Fork

Microstructure of epitaxial ferroelectric/conductive oxide heterostructures on LaAIO3(LAO) and Si substrates have been studied by conventional and high resolution transmission electron microscopy. The epitaxial films have a wide range of potential applications in areas such as non-volatile memory devices, electro-optic devices and pyroelectric detectors. For applications such as electro-optic devices the films must be single crystal and for applications such as nonvolatile memory devices and pyroelectric devices single crystal films will enhance the performance of the devices. The ferroelectric films studied are Pb(Zr0.2Ti0.8)O3(PLZT), PbTiO3(PT), BiTiO3(BT) and Pb0.9La0.1(Zr0.2Ti0.8)0.975O3(PLZT).Electrical contact to ferroelectric films is commonly made with metals such as Pt. Metals generally have a large difference in work function compared to the work function of the ferroelectric oxides. This results in a Schottky barrier at the interface and the interfacial space charge is believed to responsible for domain pinning and degradation in the ferroelectric properties resulting in phenomenon such as fatigue.


2001 ◽  
Vol 73 (2) ◽  
pp. 147 ◽  
Author(s):  
Yukihito Kabuyama ◽  
Miwako K. Homma ◽  
Masayuki Sekimata ◽  
Yoshimi Homma

Author(s):  
Myeongwoon JEON ◽  
Kyungchul KIM ◽  
Sungkyu CHUNG ◽  
Seungjae CHUNG ◽  
Beomju SHIN ◽  
...  

2021 ◽  
Author(s):  
Garrett C. Mathews ◽  
Matthew Blaisdell ◽  
Aaron I. Lemcherfi ◽  
Carson D. Slabaugh ◽  
Christopher S. Goldenstein

Author(s):  
Julie Segal ◽  
Arman Sagatelian ◽  
Bob Hodgkins ◽  
Tom Ho ◽  
Ben Chu ◽  
...  

Abstract Physical failure analysis (FA) of integrated circuit devices that fail electrical test is an important part of the yield improvement process. This article describes how the analysis of existing data from arrayed devices can be used to replace physical FA of some electrical test failures, and increase the value of physical FA results. The discussion is limited to pre-repair results. The key is to use classified bitmaps and determine which signature classification correlates to which type of in-line defect. Using this technique, physical failure mechanisms can be determined for large numbers of failures on a scale that would be unfeasible with de-processing and physical FA. If the bitmaps are classified, two-way correlation can be performed: in-line defect to bitmap failure, as well as bitmap signature to in-line defect. Results also demonstrate the value of analyzing memory devices failures, even those that can be repaired, to gain understanding of defect mechanisms.


Author(s):  
Roger Alvis ◽  
Jeff Blackwood ◽  
Sang-Hoon Lee ◽  
Matthew Bray

Abstract Semiconductor devices with critical dimensions less than 20nm are now being manufactured in volume. A challenge facing the failure analysis and process-monitoring community is two-fold. The first challenge of TEM sample prep of such small devices is that the basic need to end-point on a feature-of-interest pushes the imaging limit of the instrument being used to prepare the lamella. The second challenge posed by advanced devices is to prepare an artifact-free lamella from non-planar devices such as finFETs as well as from structures incorporating ‘non-traditional’ materials. These challenges are presently overcome in many advanced logic and memory devices in the focused ion beam-based TEM sample preparation processes by inverting the specimen prior to thinning to electron transparency. This paper reports a highthroughput method for the routine preparation of artifact-free TEM lamella of 20nm thickness, or less.


Author(s):  
S.-S. Lee ◽  
J.-S. Seo ◽  
N.-S. Cho ◽  
S. Daniel

Abstract Both photo- and thermal emission analysis techniques are used from the backside of the die colocate defect sites. The technique is important in that process and package technologies have made front-side analysis difficult or impossible. Several test cases are documented. Intensity attenuation through the bulk of the silicon does not compromise the usefulness of the technique in most cases.


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