A fully integrated front-end for 2.4 GHz low power applications

Author(s):  
F. Villain ◽  
J. Chiesa
Keyword(s):  
1998 ◽  
Vol 45 (4) ◽  
pp. 2272-2278 ◽  
Author(s):  
J. Vandenbussche ◽  
F. Leyn ◽  
G. Van der Plas ◽  
G. Gielen ◽  
W. Sansen

VLSI Design ◽  
2007 ◽  
Vol 2007 ◽  
pp. 1-13 ◽  
Author(s):  
Jianhong Xiao ◽  
Guang Zhang ◽  
Tianwei Li ◽  
Jose Silva-Martinez

A low-cost low-power DTV tuner for current digital television application is described. In order to increase integration level and reduce power consumption for off-air DTV tuner application, an SAW-filterless tuner front-end architecture is adopted. As a part of the concept, key building blocks for this architecture are implemented on a main stream 0.35 μm CMOS technology. Experimental measurements for the prototype chip validate the system architecture; the prototype consumes 300 mw and achieves 45 dB of image rejection ratio within the entire 750 MHz frequency band.


2016 ◽  
Vol 25 (3) ◽  
pp. 424-431
Author(s):  
Zuochen Shi ◽  
Yintang Yang ◽  
Di Li ◽  
Yang Liu

2010 ◽  
Vol E93-C (6) ◽  
pp. 785-795
Author(s):  
Sung-Jin KIM ◽  
Minchang CHO ◽  
SeongHwan CHO
Keyword(s):  
Rfid Tag ◽  

2021 ◽  
Vol 11 (2) ◽  
pp. 22
Author(s):  
Umberto Ferlito ◽  
Alfio Dario Grasso ◽  
Michele Vaiana ◽  
Giuseppe Bruno

Charge-Based Capacitance Measurement (CBCM) technique is a simple but effective technique for measuring capacitance values down to the attofarad level. However, when adopted for fully on-chip implementation, this technique suffers output offset caused by mismatches and process variations. This paper introduces a novel method that compensates the offset of a fully integrated differential CBCM electronic front-end. After a detailed theoretical analysis of the differential CBCM topology, we present and discuss a modified architecture that compensates mismatches and increases robustness against mismatches and process variations. The proposed circuit has been simulated using a standard 130-nm technology and shows a sensitivity of 1.3 mV/aF and a 20× reduction of the standard deviation of the differential output voltage as compared to the traditional solution.


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