scholarly journals Low-Power Fully Integrated CMOS DTV Tuner Front-End for ATSC Terrestrial Broadcasting

VLSI Design ◽  
2007 ◽  
Vol 2007 ◽  
pp. 1-13 ◽  
Author(s):  
Jianhong Xiao ◽  
Guang Zhang ◽  
Tianwei Li ◽  
Jose Silva-Martinez
Keyword(s):  
Low Power ◽  
Low Cost ◽  
Building Blocks ◽  
Cmos Technology ◽  
Digital Television ◽  
Main Stream ◽  
Image Rejection ◽  
Fully Integrated ◽  
Front End ◽  
Image Rejection Ratio

A low-cost low-power DTV tuner for current digital television application is described. In order to increase integration level and reduce power consumption for off-air DTV tuner application, an SAW-filterless tuner front-end architecture is adopted. As a part of the concept, key building blocks for this architecture are implemented on a main stream 0.35 μm CMOS technology. Experimental measurements for the prototype chip validate the system architecture; the prototype consumes 300 mw and achieves 45 dB of image rejection ratio within the entire 750 MHz frequency band.

scholarly journals Design of a very low-power, low-cost 60 GHz receiver front-end implemented in 65 nm CMOS technology

2011 ◽  
Vol 3 (2) ◽  
pp. 131-138 ◽  
Author(s):  
Michael Kraemer ◽  
Daniela Dragomirescu ◽  
Robert Plana
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Noise Figure ◽  
Low Cost ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Voltage Controlled Oscillator ◽  
60 Ghz ◽  
Front End

The research on the design of receiver front-ends for very high data-rate communication in the 60 GHz band in nanoscale Complementary Metal Oxide Semiconductor (CMOS) technologies is going on for some time now. Although a multitude of 60 GHz front-ends have been published in recent years, they are not consequently optimized for low power consumption. Thus, these front-ends dissipate too much power for battery-powered applications like handheld devices, mobile phones, and wireless sensor networks. This article describes the design of a direct conversion receiver front-end that addresses the issue of power consumption, while at the same time permitting low cost (due to area minimization by the use of spiral inductors). It is implemented in a 65 nm CMOS technology. The realized front-end achieves a record power consumption of only 43 mW including low-noise amplifier (LNA), mixer, a voltage controlled oscillator (VCO), a local oscillator (LO) buffer, and a baseband buffer (without this latter buffer the power consumption is even lower, only 29 mW). Its pad-limited size is 0.55 × 1 mm2. At the same time, the front-end achieves state-of-the-art performance with respect to its other properties: Its maximum measured power conversion gain is 30 dB, the RF and IF bandwidths are 56.5–61.5 and 0–1.5 GHz, respectively, its measured minimum noise figure is 9.2 dB, and its measured IP−1 dB is −36 dBm.

scholarly journals Analysis of Non-Idealities on CMOS Passive Mixers

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1105
Author(s):  
Antonio D. Martinez-Perez ◽  
Francisco Aznar ◽  
Guillermo Royo ◽  
Santiago Celma
Keyword(s):  
Final Section ◽  
Cmos Technology ◽  
Monte Carlo Analysis ◽  
Image Rejection ◽  
Structure Approach ◽  
Quadrature Scheme ◽  
Current State ◽  
The Cost ◽  
Image Rejection Ratio ◽  
The Ideal

In the current state of the art, WiFi-alike standards require achieving a high Image Rejection Ratio (IRR) while having low power consumption. Thus, quadrature structures based on passive ring mixers offer an attractive and widely used solution, as they can achieve a high IRR while being a passive block. However, it is not easy for the designer to know when a simple quadrature scheme is enough and when they should aim for a double quadrature structure approach, as the latter can improve the performance at the cost of requiring more area and complexity. This study focuses on the IRR, which crucially depends on the symmetry between the I and Q branches. Non-idealities (component mismatches, parasitics, etc.) will degrade the ideal balance by affecting the mixer and/or following/previous stages. This paper analyses the effect of imbalances, providing the constraints for obtaining a 40 dB IRR in the case of a conversion from a one-hundred-megahertz signal to the five-gigahertz range (upconversion) and vice versa (downconversion) for simple and double quadrature schemes. All simulations were carried out with complete device models from 65 nm standard CMOS technology and also a post-layout Monte Carlo analysis was included for mismatch analysis. The final section includes guidelines to help designers choose the most adequate scheme for each case.

A fully integrated low-power CMOS particle detector front-end for space applications

1998 ◽  
Vol 45 (4) ◽  
pp. 2272-2278 ◽  
Author(s):  
J. Vandenbussche ◽  
F. Leyn ◽  
G. Van der Plas ◽  
G. Gielen ◽  
W. Sansen
Keyword(s):  
Low Power ◽  
Particle Detector ◽  
Space Applications ◽  
Fully Integrated ◽  
Front End ◽  
Low Power Cmos

A 110–125 GHz 27.5 dB Gain Low-power I/Q Receiver Front-end in 65 nm CMOS Technology

2018 ◽  
Author(s):  
Chae Jun Lee ◽  
Dong Min Kang ◽  
Joon Hyung Kim ◽  
Chul Woo Byeon ◽  
Chul Soon Park
Keyword(s):  
Low Power ◽  
Cmos Technology ◽  
Front End

scholarly journals BUILDING BLOCKS FOR A 24 GHZ PHASED-ARRAY FRONT-END IN CMOS TECHNOLOGY FOR SMART STREETLIGHTS

2014 ◽  
Vol 61 ◽  
pp. 99-119
Author(s):  
Ban Wang ◽  
Gabriele Tasselli ◽  
Cyril Botteron ◽  
Pierre-Andre Farine
Keyword(s):  
Phased Array ◽  
Building Blocks ◽  
Cmos Technology ◽  
Front End ◽  
24 Ghz

scholarly journals Low power and high speed GDI based convolution using Vedic multiplier

2018 ◽  
Vol 7 (2.7) ◽  
pp. 733
Author(s):  
C Priyanka ◽  
N Manoj Kumar ◽  
L Sai Priya ◽  
B Vaishnavi ◽  
M Rama Krishna
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
Digital Signal ◽  
Building Blocks ◽  
Cmos Technology ◽  
Low Power Consumption ◽  
Basic Building Block ◽  
Extensive Area ◽  
Vedic Multiplier

Convolution is having extensive area of application in Digital Signal Processing. Convolution supports to evaluate the output of a system with arbitrary input, with information of impulse response of the system.  Linear systems features are totally stated by the systems impulse response, as ruled by the mathematics of convolution. Primary necessity of any application to work fast is that rise in the speed of their basic building block. Multiplier, adder is said to be the important building blocks in the process of convolution. As these blocks consumes plentiful time to obtain the response of the system.  Several methods are designed to progress the speed of the Multiplier and adder, among all GDI (Gate Diffusion Input) is under emphasis because of faster working and low power consumption. In this paper GDI based convolution is implemented using Vedic multiplier and adder in T-SPICE Software which increases the speed and consumes less power compared to CMOS technology. 

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